media: imx: imx7_mipi_csis: Update ISP_CONFIG macros for quad pixel mode

The i.MX8MM expands the DOUBLE_CMPNT bit in the ISP_CONFIG register into
a two bits field that support quad pixel mode in addition to the single
and double modes. Update the ISP_CONFIG register macros to support this.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rui Miguel Silva <rmfrfs@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/staging/media/imx/imx7-mipi-csis.c b/drivers/staging/media/imx/imx7-mipi-csis.c
index 4d1ac22..fe6aa1d 100644 (file)
--- a/drivers/staging/media/imx/imx7-mipi-csis.c
+++ b/drivers/staging/media/imx/imx7-mipi-csis.c
@@ -166,7 +166,9 @@
 #define MIPI_CSIS_ISP_CONFIG_CH(n)             (0x40 + (n) * 0x10)
 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK      (0xff << 24)
 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)       ((x) << 24)
-#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT          BIT(12)
+#define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE     (0 << 12)
+#define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL       (1 << 12)
+#define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD       (2 << 12)       /* i.MX8M[MNP] only */
 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT           BIT(11)
 #define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT     (0x1e << 2)
 #define MIPI_CSIS_ISPCFG_FMT_RAW8              (0x2a << 2)