panfrost: Rework the render target layout to use overlapping structs

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6980>

diff --git a/src/gallium/drivers/panfrost/pan_mfbd.c b/src/gallium/drivers/panfrost/pan_mfbd.c
index c062d52..f535173 100644 (file)
--- a/src/gallium/drivers/panfrost/pan_mfbd.c
+++ b/src/gallium/drivers/panfrost/pan_mfbd.c
@@ -226,42 +226,43 @@ panfrost_mfbd_rt_set_buf(struct pipe_surface *surf,
 
         if (rsrc->modifier == DRM_FORMAT_MOD_LINEAR) {
                 if (version >= 7)
-                        rt->writeback_block_format_v7 = MALI_BLOCK_FORMAT_V7_LINEAR;
+                        rt->bifrost_v7.writeback_block_format = MALI_BLOCK_FORMAT_V7_LINEAR;
                 else
-                        rt->writeback_block_format = MALI_BLOCK_FORMAT_LINEAR;
+                        rt->midgard.writeback_block_format = MALI_BLOCK_FORMAT_LINEAR;
 
-                rt->writeback_base = base;
-                rt->writeback_row_stride = stride;
-                rt->writeback_surface_stride = layer_stride;
+                rt->rgb.base = base;
+                rt->rgb.row_stride = stride;
+                rt->rgb.surface_stride = layer_stride;
         } else if (rsrc->modifier == DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED) {
                 if (version >= 7)
-                        rt->writeback_block_format_v7 = MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED;
+                        rt->bifrost_v7.writeback_block_format = MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED;
                 else
-                        rt->writeback_block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
+                        rt->midgard.writeback_block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
 
-                rt->writeback_base = base;
-                rt->writeback_row_stride = stride * 16;
-                rt->writeback_surface_stride = layer_stride;
+                rt->rgb.base = base;
+                rt->rgb.row_stride = stride * 16;
+                rt->rgb.surface_stride = layer_stride;
         } else if (drm_is_afbc(rsrc->modifier)) {
                 if (version >= 7)
-                        rt->writeback_block_format = MALI_BLOCK_FORMAT_V7_AFBC;
+                        rt->bifrost_v7.writeback_block_format = MALI_BLOCK_FORMAT_V7_AFBC;
                 else
-                        rt->writeback_block_format = MALI_BLOCK_FORMAT_AFBC;
+                        rt->midgard.writeback_block_format = MALI_BLOCK_FORMAT_AFBC;
 
                 unsigned header_size = rsrc->slices[level].header_size;
 
-                rt->afbc_header = base;
-                rt->afbc_chunk_size = 9;
-                rt->afbc_sparse = true;
-                rt->afbc_body = base + header_size;
-                rt->writeback_surface_stride = layer_stride;
+                rt->afbc.header = base;
+                rt->afbc.chunk_size = 9;
+                rt->afbc.body = base + header_size;
+
+                if (!(dev->quirks & IS_BIFROST))
+                        rt->midgard_afbc.sparse = true;
 
                 if (rsrc->modifier & AFBC_FORMAT_MOD_YTR)
-                        rt->afbc_yuv_transform_enable = true;
+                        rt->afbc.yuv_transform_enable = true;
 
                 /* TODO: The blob sets this to something nonzero, but it's not
                  * clear what/how to calculate/if it matters */
-                rt->afbc_body_size = 0;
+                rt->afbc.body_size = 0;
         } else {
                 unreachable("Invalid mod");
         }
@@ -286,16 +287,16 @@ panfrost_mfbd_emit_rt(struct panfrost_batch *batch,
                         rt.internal_format = MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A8;
                         rt.internal_buffer_offset = rt_offset;
                         if (version >= 7) {
-                                rt.writeback_block_format_v7 = MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED;
+                                rt.bifrost_v7.writeback_block_format = MALI_BLOCK_FORMAT_V7_TILED_U_INTERLEAVED;
                                 rt.dithering_enable = true;
                         }
                 }
 
                 if (batch->clear & (PIPE_CLEAR_COLOR0 << rt_idx)) {
-                        rt.clear_color_0 = batch->clear_color[rt_idx][0];
-                        rt.clear_color_1 = batch->clear_color[rt_idx][1];
-                        rt.clear_color_2 = batch->clear_color[rt_idx][2];
-                        rt.clear_color_3 = batch->clear_color[rt_idx][3];
+                        rt.clear.color_0 = batch->clear_color[rt_idx][0];
+                        rt.clear.color_1 = batch->clear_color[rt_idx][1];
+                        rt.clear.color_2 = batch->clear_color[rt_idx][2];
+                        rt.clear.color_3 = batch->clear_color[rt_idx][3];
                 }
         }
 }

diff --git a/src/panfrost/lib/midgard.xml b/src/panfrost/lib/midgard.xml
index a978d0a..75aa3f2 100644 (file)
--- a/src/panfrost/lib/midgard.xml
+++ b/src/panfrost/lib/midgard.xml
@@ -965,66 +965,105 @@
     <value name="Three Quarters" value="5"/>
   </enum>
 
-  <struct name="Render Target">
-    <field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
-    <field name="YUV Enable" size="1" start="0:24" type="bool"/>
-    <field name="Dithered Clear" size="1" start="0:25" type="bool"/>
-    <field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
-    <field name="Write Enable" size="1" start="1:0" type="bool"/>
-    <field name="Writeback Format" size="5" start="1:3" type="MFBD Color Format"/>
+  <struct name="Render Target Midgard Overlay" size="16">
     <field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
     <field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
-    <field name="Writeback Block Format v7" size="4" start="1:8" type="Block Format v7"/>
-    <field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
-    <field name="sRGB" size="1" start="1:14" type="bool"/>
-    <field name="Dithering Enable" size="1" start="1:15" type="bool"/>
-    <field name="Swizzle" size="12" start="1:16" type="uint"/>
     <field name="Writeback Sampling Mode" size="2" start="1:29" type="Downsampling Accumulation Mode"/>
-    <field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
     <field name="Preload Enable" size="1" start="2:0" type="bool"/>
     <field name="Unload Enable" size="1" start="2:1" type="bool"/>
     <field name="Preload Format" size="5" start="2:3" type="MFBD Color Format"/>
     <field name="Preload Endianness" size="2" start="2:8" type="RT Endianness"/>
     <field name="Preload Block Format" size="4" start="2:10" type="Block Format"/>
     <field name="Preload MSAA" size="2" start="2:14" type="MSAA"/>
-    <field name="YUV Conv K5" size="8" start="2:16" type="uint"/>
-    <field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
-    <field name="YUV Full Range" size="1" start="2:20" type="bool"/>
-    <field name="YUV Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
-    <field name="YUV Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
-    <field name="YUV Unsigned Cr Range" size="1" start="2:28" type="bool"/>
-    <field name="YUV Conv K6" size="1" start="2:24" type="YUV Conv K6"/>
-    <field name="YUV Conv K7 Clamp" size="2" start="2:25" type="YUV Conv K7 Clamp"/>
-    <field name="YUV Conv K8" size="1" start="2:27" type="YUV Conv K8"/>
-    <field name="YUV Conv Disable" size="1" start="2:31" type="bool"/>
-    <field name="YUV Conv K1" size="8" start="3:0" type="uint"/>
-    <field name="YUV Conv K2" size="8" start="3:8" type="uint"/>
-    <field name="YUV Conv K3" size="8" start="3:16" type="uint"/>
-    <field name="YUV Conv K4" size="8" start="3:24" type="uint"/>
-    <field name="YUV Plane 0 Base" size="64" start="4:0" type="address"/>
-    <field name="YUV Plane 1 Base" size="64" start="6:0" type="address"/>
-    <field name="YUV Plane 2 Base" size="64" start="8:0" type="address"/>
-    <field name="YUV Plane 0 Stride" size="32" start="10:0" type="uint"/>
-    <field name="YUV Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
-    <field name="AFBC Header" size="64" start="4:0" type="address"/>
-    <field name="AFBC Row Stride" size="13" start="6:0" type="uint"/>
-    <field name="AFBC Chunk Size" size="12" start="7:0" type="uint"/>
-    <field name="AFBC Sparse" size="1" start="7:16" type="bool"/>
-    <field name="AFBC YUV Transform Enable" size="1" start="7:17" type="bool"/>
+  </struct>
+
+  <struct name="Render Target Midgard YUV Overlay" size="16">
+    <field name="Conv K5" size="8" start="2:16" type="uint"/>
+    <field name="Conv K6" size="1" start="2:24" type="YUV Conv K6"/>
+    <field name="Conv K7 Clamp" size="2" start="2:25" type="YUV Conv K7 Clamp"/>
+    <field name="Conv K8" size="1" start="2:27" type="YUV Conv K8"/>
+    <field name="Conv Disable" size="1" start="2:31" type="bool"/>
+    <field name="Conv K1" size="8" start="3:0" type="uint"/>
+    <field name="Conv K2" size="8" start="3:8" type="uint"/>
+    <field name="Conv K3" size="8" start="3:16" type="uint"/>
+    <field name="Conv K4" size="8" start="3:24" type="uint"/>
+  </struct>
+
+  <struct name="Render Target Bifrost YUV Overlay" size="16">
+    <field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
+    <field name="Full Range" size="1" start="2:20" type="bool"/>
+    <field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
+    <field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
+    <field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
+  </struct>
+
+  <struct name="Render Target Bifrost v7 Overlay" size="16">
+    <field name="Writeback Block Format" size="4" start="1:8" type="Block Format v7"/>
+    <field name="Dithered Clear" size="1" start="0:25" type="bool"/>
+  </struct>
+
+  <struct name="Render Target Bifrost v6 Overlay" size="16">
+    <field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
+    <field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
+    <field name="Dithered Clear" size="1" start="0:25" type="bool"/>
+  </struct>
+
+  <struct name="Render Target YUV Overlay" size="16">
+    <field name="Plane 0 Base" size="64" start="4:0" type="address"/>
+    <field name="Plane 1 Base" size="64" start="6:0" type="address"/>
+    <field name="Plane 2 Base" size="64" start="8:0" type="address"/>
+    <field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
+    <field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
+  </struct>
+
+  <struct name="Render Target AFBC Overlay" size="16">
+    <field name="Header" size="64" start="4:0" type="address"/>
+    <field name="Row Stride" size="13" start="6:0" type="uint"/>
+    <field name="Chunk Size" size="12" start="7:0" type="uint"/>
+    <field name="YUV Transform Enable" size="1" start="7:17" type="bool"/>
+    <field name="Body" size="64" start="8:0" type="address"/>
+    <field name="Body Size" size="32" start="10:0" type="uint"/>
+  </struct>
+
+  <struct name="Render Target Midgard AFBC Overlay" size="16">
+    <field name="Sparse" size="1" start="7:16" type="bool"/>
+  </struct>
+
+  <struct name="Render Target Bifrost AFBC Overlay" size="16">
     <field name="AFBC Split Block Enable" size="1" start="7:18" type="bool"/>
     <field name="AFBC Wide Block Enable" size="1" start="7:19" type="bool"/>
-    <field name="AFBC Body" size="64" start="8:0" type="address"/>
-    <field name="AFBC Body Size" size="32" start="10:0" type="uint"/>
-    <field name="Writeback Base" size="64" start="8:0" type="address"/>
-    <field name="Writeback Row Stride" size="32" start="10:0" type="uint"/>
-    <field name="Writeback Surface Stride" size="32" start="11:0" type="uint"/>
-    <field name="Preload Base" size="64" start="12:0" type="address"/>
-    <field name="Preload Row Stride" size="32" start="14:0" type="uint"/>
-    <field name="Preload Surface Stride" size="32" start="15:0" type="uint"/>
-    <field name="Clear Color 0" size="32" start="12:0" type="uint"/>
-    <field name="Clear Color 1" size="32" start="13:0" type="uint"/>
-    <field name="Clear Color 2" size="32" start="14:0" type="uint"/>
-    <field name="Clear Color 3" size="32" start="15:0" type="uint"/>
+  </struct>
+
+  <struct name="RT Clear">
+    <field name="Color 0" size="32" start="0:0" type="uint"/>
+    <field name="Color 1" size="32" start="1:0" type="uint"/>
+    <field name="Color 2" size="32" start="2:0" type="uint"/>
+    <field name="Color 3" size="32" start="3:0" type="uint"/>
+  </struct>
+
+  <struct name="Render Target">
+    <field name="Midgard" size="512" start="0:0" type="Render Target Midgard Overlay"/>
+    <field name="Bifrost v6" size="512" start="0:0" type="Render Target Bifrost v6 Overlay"/>
+    <field name="Bifrost v7" size="512" start="0:0" type="Render Target Bifrost v7 Overlay"/>
+    <field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
+    <field name="Midgard YUV" size="512" start="0:0" type="Render Target Midgard YUV Overlay"/>
+    <field name="Bifrost YUV" size="512" start="0:0" type="Render Target Bifrost YUV Overlay"/>
+    <field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
+    <field name="Midgard AFBC" size="512" start="0:0" type="Render Target Midgard AFBC Overlay"/>
+    <field name="Bifrost AFBC" size="512" start="0:0" type="Render Target Bifrost AFBC Overlay"/>
+    <field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
+    <field name="YUV Enable" size="1" start="0:24" type="bool"/>
+    <field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
+    <field name="Write Enable" size="1" start="1:0" type="bool"/>
+    <field name="Writeback Format" size="5" start="1:3" type="MFBD Color Format"/>
+    <field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
+    <field name="sRGB" size="1" start="1:14" type="bool"/>
+    <field name="Dithering Enable" size="1" start="1:15" type="bool"/>
+    <field name="Swizzle" size="12" start="1:16" type="uint"/>
+    <field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
+    <field name="RGB" size="128" start="8:0" type="RT Buffer"/>
+    <field name="Midgard Preload" size="128" start="12:0" type="RT Buffer"/>
+    <field name="Clear" size="128" start="12:0" type="RT Clear"/>
   </struct>
 
   <enum name="Pre Post Frame Shader Mode">