clk: bcm2835: remove pllb

Commit 2256d89333bd17b8b56b42734a7e1046d52f7fc3 upstream.

Raspberry Pi's firmware controls this pll, we should use the firmware
interface to access it.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 94d239d..d460876 100644 (file)
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1755,32 +1755,10 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
                .fixed_divider = 1,
                .flags = CLK_SET_RATE_PARENT),
 
-       /* PLLB is used for the ARM's clock. */
-       [BCM2835_PLLB]          = REGISTER_PLL(
-               SOC_ALL,
-               .name = "pllb",
-               .cm_ctrl_reg = CM_PLLB,
-               .a2w_ctrl_reg = A2W_PLLB_CTRL,
-               .frac_reg = A2W_PLLB_FRAC,
-               .ana_reg_base = A2W_PLLB_ANA0,
-               .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
-               .lock_mask = CM_LOCK_FLOCKB,
-
-               .ana = &bcm2835_ana_default,
-
-               .min_rate = 600000000u,
-               .max_rate = 3000000000u,
-               .max_fb_rate = BCM2835_MAX_FB_RATE),
-       [BCM2835_PLLB_ARM]      = REGISTER_PLL_DIV(
-               SOC_ALL,
-               .name = "pllb_arm",
-               .source_pll = "pllb",
-               .cm_reg = CM_PLLB,
-               .a2w_reg = A2W_PLLB_ARM,
-               .load_mask = CM_PLLB_LOADARM,
-               .hold_mask = CM_PLLB_HOLDARM,
-               .fixed_divider = 1,
-               .flags = CLK_SET_RATE_PARENT),
+       /*
+        * PLLB is used for the ARM's clock. Controlled by firmware, see
+        * clk-raspberrypi.c.
+        */
 
        /*
         * PLLC is the core PLL, used to drive the core VPU clock.