* arm.c (thumb_expand_movstrqi): Rewrite to support SSA form.
(thumb_output_move_mem_multiple): Support new insn format.
* arm.md (movmem12b): Use SSA compatible format.
(movmem8b): Likewise.
From-SVN: r36809
2000-10-09 Richard Earnshaw <rearnsha@arm.com>
+ * arm.c (thumb_expand_movstrqi): Rewrite to support SSA form.
+ (thumb_output_move_mem_multiple): Support new insn format.
+ * arm.md (movmem12b): Use SSA compatible format.
+ (movmem8b): Likewise.
+
+2000-10-09 Richard Earnshaw <rearnsha@arm.com>
+
* arm.md (predicable): New attribute, default to "no".
(all patterns): Mark as predicable if appropriate.
(conditional execution splits): Split using predication format.
switch (n)
{
case 2:
- if (REGNO (operands[2]) > REGNO (operands[3]))
+ if (REGNO (operands[4]) > REGNO (operands[5]))
{
- tmp = operands[2];
- operands[2] = operands[3];
- operands[3] = tmp;
+ tmp = operands[4];
+ operands[4] = operands[5];
+ operands[5] = tmp;
}
- output_asm_insn ("ldmia\t%1!, {%2, %3}", operands);
- output_asm_insn ("stmia\t%0!, {%2, %3}", operands);
+ output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
+ output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
break;
case 3:
- if (REGNO (operands[2]) > REGNO (operands[3]))
+ if (REGNO (operands[4]) > REGNO (operands[5]))
{
- tmp = operands[2];
- operands[2] = operands[3];
- operands[3] = tmp;
+ tmp = operands[4];
+ operands[4] = operands[5];
+ operands[5] = tmp;
}
- if (REGNO (operands[3]) > REGNO (operands[4]))
+ if (REGNO (operands[5]) > REGNO (operands[6]))
{
- tmp = operands[3];
- operands[3] = operands[4];
- operands[4] = tmp;
+ tmp = operands[5];
+ operands[5] = operands[6];
+ operands[6] = tmp;
}
- if (REGNO (operands[2]) > REGNO (operands[3]))
+ if (REGNO (operands[4]) > REGNO (operands[5]))
{
- tmp = operands[2];
- operands[2] = operands[3];
- operands[3] = tmp;
+ tmp = operands[4];
+ operands[4] = operands[5];
+ operands[5] = tmp;
}
- output_asm_insn ("ldmia\t%1!, {%2, %3, %4}", operands);
- output_asm_insn ("stmia\t%0!, {%2, %3, %4}", operands);
+ output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
+ output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
break;
default:
while (len >= 12)
{
- emit_insn (gen_movmem12b (out, in));
+ emit_insn (gen_movmem12b (out, in, out, in));
len -= 12;
}
if (len >= 8)
{
- emit_insn (gen_movmem8b (out, in));
+ emit_insn (gen_movmem8b (out, in, out, in));
len -= 8;
}
;; Block-move insns
(define_insn "movmem12b"
- [(set (mem:SI (match_operand:SI 0 "register_operand" "+&l"))
- (mem:SI (match_operand:SI 1 "register_operand" "+&l")))
- (set (mem:SI (plus:SI (match_dup 0) (const_int 4)))
- (mem:SI (plus:SI (match_dup 1) (const_int 4))))
- (set (mem:SI (plus:SI (match_dup 0) (const_int 8)))
- (mem:SI (plus:SI (match_dup 1) (const_int 8))))
- (set (match_dup 0) (plus:SI (match_dup 0) (const_int 12)))
- (set (match_dup 1) (plus:SI (match_dup 1) (const_int 12)))
- (clobber (match_scratch:SI 2 "=&l"))
- (clobber (match_scratch:SI 3 "=&l"))
- (clobber (match_scratch:SI 4 "=&l"))]
+ [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
+ (mem:SI (match_operand:SI 3 "register_operand" "1")))
+ (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+ (mem:SI (plus:SI (match_dup 3) (const_int 4))))
+ (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+ (mem:SI (plus:SI (match_dup 3) (const_int 8))))
+ (set (match_operand:SI 0 "register_operand" "=l")
+ (plus:SI (match_dup 2) (const_int 12)))
+ (set (match_operand:SI 1 "register_operand" "=l")
+ (plus:SI (match_dup 3) (const_int 12)))
+ (clobber (match_scratch:SI 4 "=&l"))
+ (clobber (match_scratch:SI 5 "=&l"))
+ (clobber (match_scratch:SI 6 "=&l"))]
"TARGET_THUMB"
"* return thumb_output_move_mem_multiple (3, operands);"
[(set_attr "length" "4")
)
(define_insn "movmem8b"
- [(set (mem:SI (match_operand:SI 0 "register_operand" "+&l"))
- (mem:SI (match_operand:SI 1 "register_operand" "+&l")))
- (set (mem:SI (plus:SI (match_dup 0) (const_int 4)))
- (mem:SI (plus:SI (match_dup 1) (const_int 4))))
- (set (match_dup 0) (plus:SI (match_dup 0) (const_int 8)))
- (set (match_dup 1) (plus:SI (match_dup 1) (const_int 8)))
- (clobber (match_scratch:SI 2 "=&l"))
- (clobber (match_scratch:SI 3 "=&l"))]
+ [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
+ (mem:SI (match_operand:SI 3 "register_operand" "1")))
+ (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+ (mem:SI (plus:SI (match_dup 3) (const_int 4))))
+ (set (match_operand:SI 0 "register_operand" "=l")
+ (plus:SI (match_dup 2) (const_int 8)))
+ (set (match_operand:SI 1 "register_operand" "=l")
+ (plus:SI (match_dup 3) (const_int 8)))
+ (clobber (match_scratch:SI 4 "=&l"))
+ (clobber (match_scratch:SI 5 "=&l"))]
"TARGET_THUMB"
"* return thumb_output_move_mem_multiple (2, operands);"
[(set_attr "length" "4")