(ashlsi3, lshrsi3, ashrsi3): Only output low-order five bits for

!TARGET_POWER case.

From-SVN: r7751

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index da15d90..9915670 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2115,7 +2115,7 @@
        (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "! TARGET_POWER"
-  "slw%I2 %0,%1,%2"
+  "slw%I2 %0,%1,%h2"
   [(set_attr "length" "8")])
 
 (define_insn ""
@@ -2138,7 +2138,7 @@
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   "! TARGET_POWER"
-  "slw%I2. %3,%1,%2"
+  "slw%I2. %3,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -2163,7 +2163,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (ashift:SI (match_dup 1) (match_dup 2)))]
   "! TARGET_POWER"
-  "slw%I2. %0,%1,%2"
+  "slw%I2. %0,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -2230,7 +2230,7 @@
        (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "! TARGET_POWER"
-  "srw%I2 %0,%1,%2")
+  "srw%I2 %0,%1,%h2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -2252,7 +2252,7 @@
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   "! TARGET_POWER"
-  "srw%I2. %3,%1,%2"
+  "srw%I2. %3,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -2277,7 +2277,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (lshiftrt:SI (match_dup 1) (match_dup 2)))]
   "! TARGET_POWER"
-  "srw%I2. %0,%1,%2"
+  "srw%I2. %0,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -2442,7 +2442,7 @@
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   "! TARGET_POWER"
-  "sraw%I2 %0,%1,%2")
+  "sraw%I2 %0,%1,%h2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
@@ -2464,7 +2464,7 @@
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   "! TARGET_POWER"
-  "sraw%I2. %3,%1,%2"
+  "sraw%I2. %3,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
@@ -2489,7 +2489,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
   "! TARGET_POWER"
-  "sraw%I2. %0,%1,%2"
+  "sraw%I2. %0,%1,%h2"
   [(set_attr "type" "delayed_compare")])
 \f
 ;; Floating-point insns, excluding normal data motion.