scsi: hisi_sas: Make phy index variable name consistent

We use "phy_id" to identify phy in the BIST code but the rest of code
always uses "phy_no". Change it for consistency.

Link: https://lore.kernel.org/r/1598958790-232272-5-git-send-email-john.garry@huawei.com
Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index b7d94f2..8a5c6f5 100644 (file)
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -2971,42 +2971,42 @@ static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
 {
        u32 reg_val;
-       int phy_id = hisi_hba->debugfs_bist_phy_no;
+       int phy_no = hisi_hba->debugfs_bist_phy_no;
 
        /* disable PHY */
-       hisi_sas_phy_enable(hisi_hba, phy_id, 0);
+       hisi_sas_phy_enable(hisi_hba, phy_no, 0);
 
        /* disable ALOS */
-       reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG);
+       reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
        reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
-       hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val);
+       hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
 }
 
 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
 {
        u32 reg_val;
-       int phy_id = hisi_hba->debugfs_bist_phy_no;
+       int phy_no = hisi_hba->debugfs_bist_phy_no;
 
        /* disable loopback */
-       reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL);
+       reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
        reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
                     CFG_BIST_TEST_MSK);
-       hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL, reg_val);
+       hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
 
        /* enable ALOS */
-       reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG);
+       reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
        reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
-       hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val);
+       hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
 
        /* restore the linkrate */
-       reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, PROG_PHY_LINK_RATE);
+       reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
        /* init OOB link rate as 1.5 Gbits */
        reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
        reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
-       hisi_sas_phy_write32(hisi_hba, phy_id, PROG_PHY_LINK_RATE, reg_val);
+       hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
 
        /* enable PHY */
-       hisi_sas_phy_enable(hisi_hba, phy_id, 1);
+       hisi_sas_phy_enable(hisi_hba, phy_no, 1);
 }
 
 #define SAS_PHY_BIST_CODE_INIT 0x1
@@ -3015,28 +3015,28 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
 {
        u32 reg_val, mode_tmp;
        u32 linkrate = hisi_hba->debugfs_bist_linkrate;
-       u32 phy_id = hisi_hba->debugfs_bist_phy_no;
+       u32 phy_no = hisi_hba->debugfs_bist_phy_no;
        u32 code_mode = hisi_hba->debugfs_bist_code_mode;
        u32 path_mode = hisi_hba->debugfs_bist_mode;
        struct device *dev = hisi_hba->dev;
 
-       dev_info(dev, "BIST info:linkrate=%d phy_id=%d code_mode=%d path_mode=%d\n",
-                linkrate, phy_id, code_mode, path_mode);
+       dev_info(dev, "BIST info:linkrate=%d phy_no=%d code_mode=%d path_mode=%d\n",
+                linkrate, phy_no, code_mode, path_mode);
        mode_tmp = path_mode ? 2 : 1;
        if (enable) {
                /* some preparations before bist test */
                hisi_sas_bist_test_prep_v3_hw(hisi_hba);
 
                /* set linkrate of bit test*/
-               reg_val = hisi_sas_phy_read32(hisi_hba, phy_id,
+               reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
                                              PROG_PHY_LINK_RATE);
                reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
                reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
-               hisi_sas_phy_write32(hisi_hba, phy_id,
-                                    PROG_PHY_LINK_RATE, reg_val);
+               hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
+                                    reg_val);
 
                /* set code mode of bit test */
-               reg_val = hisi_sas_phy_read32(hisi_hba, phy_id,
+               reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
                                              SAS_PHY_BIST_CTRL);
                reg_val &= ~(CFG_BIST_MODE_SEL_MSK |
                                CFG_LOOP_TEST_MODE_MSK |
@@ -3046,28 +3046,28 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
                reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
                            (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
                            CFG_BIST_TEST_MSK);
-               hisi_sas_phy_write32(hisi_hba, phy_id,
+               hisi_sas_phy_write32(hisi_hba, phy_no,
                                     SAS_PHY_BIST_CTRL, reg_val);
 
                /* set the bist init value */
-               hisi_sas_phy_write32(hisi_hba, phy_id,
+               hisi_sas_phy_write32(hisi_hba, phy_no,
                                     SAS_PHY_BIST_CODE,
                                     SAS_PHY_BIST_CODE_INIT);
-               hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CODE1,
+               hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CODE1,
                                     SAS_PHY_BIST_CODE1_INIT);
 
                mdelay(100);
                reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
-               hisi_sas_phy_write32(hisi_hba, phy_id,
+               hisi_sas_phy_write32(hisi_hba, phy_no,
                                     SAS_PHY_BIST_CTRL, reg_val);
 
                /* clear error bit */
                mdelay(100);
-               hisi_sas_phy_read32(hisi_hba, phy_id, SAS_BIST_ERR_CNT);
+               hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
        } else {
                /* disable bist test and recover it */
                hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
-                               phy_id, SAS_BIST_ERR_CNT);
+                               phy_no, SAS_BIST_ERR_CNT);
                hisi_sas_bist_test_restore_v3_hw(hisi_hba);
        }