[Hexagon] Remove {{ *}} from testcases

The spaces in the instructions are now consistent.

llvm-svn: 326829

diff --git a/llvm/test/CodeGen/Hexagon/absaddr-store.ll b/llvm/test/CodeGen/Hexagon/absaddr-store.ll
index dac8607d88db66c216df45ce1b5fe8f910a90416..88af3de58385dc23a496a1c4854a17ed558f438a 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/absaddr-store.ll
+++ b/llvm/test/CodeGen/Hexagon/absaddr-store.ll
@@ -10,7 +10,7 @@
 @d = external global i64
 
 define zeroext i8 @absStoreByte() nounwind {
-; CHECK: memb(##b1){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: memb(##b1) = r{{[0-9]+}}
 entry:
   %0 = load i8, i8* @b0, align 1
   %conv = zext i8 %0 to i32
@@ -21,7 +21,7 @@ entry:
 }
 
 define signext i16 @absStoreHalf() nounwind {
-; CHECK: memh(##c1){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: memh(##c1) = r{{[0-9]+}}
 entry:
   %0 = load i16, i16* @c0, align 2
   %conv = sext i16 %0 to i32
@@ -32,7 +32,7 @@ entry:
 }
 
 define i32 @absStoreWord() nounwind {
-; CHECK: memw(##a1){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: memw(##a1) = r{{[0-9]+}}
 entry:
   %0 = load i32, i32* @a0, align 4
   %mul = mul nsw i32 100, %0
@@ -41,7 +41,7 @@ entry:
 }
 
 define void @absStoreDouble() nounwind {
-; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
+; CHECK: memd(##d) = r{{[0-9]+}}:{{[0-9]+}}
 entry:
   store i64 100, i64* @d, align 8
   ret void

diff --git a/llvm/test/CodeGen/Hexagon/absimm.ll b/llvm/test/CodeGen/Hexagon/absimm.ll
index e67af5e8fef9084b36dcef7b36c30ef19c802c84..232b7221d0008c19e397cb70d6f421a0b11b692c 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/absimm.ll
+++ b/llvm/test/CodeGen/Hexagon/absimm.ll
@@ -3,7 +3,7 @@
 ; with immediate value.
 
 define i32 @f1(i32 %i) nounwind {
-; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: memw(##786432) = r{{[0-9]+}}
 entry:
   store volatile i32 %i, i32* inttoptr (i32 786432 to i32*), align 262144
   ret i32 %i
@@ -11,7 +11,7 @@ entry:
 
 define i32* @f2(i32* nocapture %i) nounwind {
 entry:
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432)
+; CHECK: r{{[0-9]+}} = memw(##786432)
   %0 = load volatile i32, i32* inttoptr (i32 786432 to i32*), align 262144
   %1 = inttoptr i32 %0 to i32*
   ret i32* %1

diff --git a/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll b/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
index 9bd010d52364c1c8a410215d26ec6986f6f1b2d2..0727c7f549bbb5105dabee518c01a2aad7d0f083 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
+++ b/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
@@ -4,7 +4,7 @@
 ; calculation.
 ;
 
-; CHECK: r0 = memub(r{{[0-9]+}}<<#3{{ *}}+{{ *}}##the_global+516)
+; CHECK: r0 = memub(r{{[0-9]+}}<<#3+##the_global+516)
 
 %0 = type { [3 x %1] }
 %1 = type { %2, i8, i8, i8, i8, i8, [4 x i8], i8, [10 x i8], [10 x i8], [10 x i8], i8, [3 x %4], i16, i16, i16, i16, i32, i8, [4 x i8], i8, i8, i8, i8, %5, i8, i8, i8, i8, i8, i16, i8, i8, i8, i16, i16, i8, i8, [2 x i8], [2 x i8], i8, i8, i8, i8, i8, i16, i16, i8, i8, i8, i8, i8, i8, %9, i8, [6 x [2 x i8]], i16, i32, %10, [28 x i8], [4 x %17] }

diff --git a/llvm/test/CodeGen/Hexagon/always-ext.ll b/llvm/test/CodeGen/Hexagon/always-ext.ll
index 3bf465b6a513a97a330f82182488b444425019f3..4b2c915333c440b8b590d3637188816be730c6aa 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/always-ext.ll
+++ b/llvm/test/CodeGen/Hexagon/always-ext.ll
@@ -7,7 +7,7 @@
 ; CHECK: {
 ; CHECK-NOT: call abort
 ; CHECK: memw(##0)
-; CHECK: memw(r{{[0-9+]}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##4)
+; CHECK: memw(r{{[0-9+]}}<<#2+##4)
 ; CHECK: }
 
 %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { i8*, void (%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*)*, i32, i32, i8*, [23 x i32]* }

diff --git a/llvm/test/CodeGen/Hexagon/bit-loop.ll b/llvm/test/CodeGen/Hexagon/bit-loop.ll
index 74a1a276115d30f6d097cb2fea6e8a39c514a7e7..021890d627c60a257b05f63557bdad04f89b540b 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/bit-loop.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-loop.ll
@@ -1,10 +1,9 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK-DAG: memh(r{{[0-9]+}}+#0) = r{{[0-9]+}}
 ; CHECK-DAG: memh(r{{[0-9]+}}+#2) = r{{[0-9]+}}.h
 ; CHECK-DAG: memh(r{{[0-9]+}}+#4) = r{{[0-9]+}}
 ; CHECK-DAG: memh(r{{[0-9]+}}+#6) = r{{[0-9]+}}.h
 
-target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
 target triple = "hexagon"
 
 ; Function Attrs: nounwind

diff --git a/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll b/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
index b542308abd3e5464b4ec077dc300b9785bc2803d..eac372d114b7f92580ce9a6d50a4a937352ec9ae 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check for the immediate offset.  It must be a multiple of 8.
-; CHECK: dcfetch({{.*}}+{{ *}}#8)
+; CHECK: dcfetch({{.*}}+#8)
 ; In 6.2 (which supports v4+ only), we generate indexed dcfetch in all cases
 ; (unlike in 6.1, which supported v2, where dcfetch did not allow an immediate
 ; offset).
@@ -9,7 +9,7 @@
 ; possible one).  Check for #0 anyways, if the test fails with a false
 ; positive, the second check can be eliminated, or rewritten, and in the
 ; meantime it can help catch real problems.
-; CHECK: dcfetch({{.*}}+{{ *}}#0)
+; CHECK: dcfetch({{.*}}+#0)
 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
 target triple = "hexagon"
 

diff --git a/llvm/test/CodeGen/Hexagon/cext-check.ll b/llvm/test/CodeGen/Hexagon/cext-check.ll
index 46e816d15e5f9242a93158a9104a6786c1ea5a7a..597136d97b0a63d60f31f3f91888595424201fed 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/cext-check.ll
+++ b/llvm/test/CodeGen/Hexagon/cext-check.ll
@@ -2,10 +2,10 @@
 ; Check that we constant extended instructions only when necessary.
 
 define i32 @cext_test1(i32* %a) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##8000)
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000)
-; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##4092)
-; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##8000)
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},##300000)
+; CHECK-NOT: r{{[0-9]+}} = memw(r{{[0-9]+}}+##4092)
+; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},##300)
 entry:
   %0 = load i32, i32* %a, align 4
   %tobool = icmp ne i32 %0, 0
@@ -29,10 +29,10 @@ return:
 }
 
 define i32 @cext_test2(i8* %a) nounwind {
-; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+{{ *}}##1023)
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000)
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}##1024)
-; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##6000)
+; CHECK-NOT: r{{[0-9]+}} = memub(r{{[0-9]+}}+##1023)
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},##300000)
+; CHECK: r{{[0-9]+}} = memub(r{{[0-9]+}}+##1024)
+; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},##6000)
 entry:
   %tobool = icmp ne i8* %a, null
   br i1 %tobool, label %if.then, label %if.end

diff --git a/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll b/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
index 9f03ef1309ecc487ec061d11bdd5193028a1c486..58e07ddccffc1e414da20db936fc7ee1d38af03e 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
+++ b/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
@@ -2,8 +2,8 @@
 ; Check that the packetizer generates valid packets with constant
 ; extended add and base+offset store instructions.
 
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}},{{ *}}##200000)
-; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}##12000){{ *}}={{ *}}r{{[0-9]+}}.new
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},##200000)
+; CHECK-NEXT: memw(r{{[0-9]+}}+##12000) = r{{[0-9]+}}.new
 ; CHECK-NEXT: }
 
 define void @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind {

diff --git a/llvm/test/CodeGen/Hexagon/cext.ll b/llvm/test/CodeGen/Hexagon/cext.ll
index 6daba8cc9599d08ee0b40a70190390e36ab0385f..5390657fd9a2f9923fda77b0cf5c315560a65bb3 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/cext.ll
+++ b/llvm/test/CodeGen/Hexagon/cext.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: memub(r{{[0-9]+}}{{ *}}<<{{ *}}#1{{ *}}+{{ *}}##a)
+; CHECK: memub(r{{[0-9]+}}<<#1+##a)
 
 @a = external global [5 x [2 x i8]]
 

diff --git a/llvm/test/CodeGen/Hexagon/cexti16.ll b/llvm/test/CodeGen/Hexagon/cexti16.ll
index 465cfe400719eb3953195c50e0dfc64f5a86a397..56e1e49271308faa0da94ceb6708d99f8740862c 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/cexti16.ll
+++ b/llvm/test/CodeGen/Hexagon/cexti16.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: memuh(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##a)
+; CHECK: memuh(r{{[0-9]+}}<<#2+##a)
 
 @a = external global [5 x [2 x i16]]
 

diff --git a/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll b/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll
index d0df168151317ca4cdd30907685c41d40b161912..a3658fb0c830002f8b77e9a89ccff4bc7d071b4f 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll
+++ b/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll
@@ -2,7 +2,7 @@
 ; Check that we generate compare to general register.
 
 define i32 @compare1(i32 %a) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}#120)
+; CHECK: r{{[0-9]+}} = cmp.eq(r{{[0-9]+}},#120)
 entry:
   %cmp = icmp eq i32 %a, 120
   %conv = zext i1 %cmp to i32
@@ -10,7 +10,7 @@ entry:
 }
 
 define i32 @compare2(i32 %a) nounwind readnone {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#120)
+; CHECK: r{{[0-9]+}} = !cmp.eq(r{{[0-9]+}},#120)
 entry:
   %cmp = icmp ne i32 %a, 120
   %conv = zext i1 %cmp to i32
@@ -18,7 +18,7 @@ entry:
 }
 
 define i32 @compare3(i32 %a, i32 %b) nounwind readnone {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = cmp.eq(r{{[0-9]+}},r{{[0-9]+}})
 entry:
   %cmp = icmp eq i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -26,7 +26,7 @@ entry:
 }
 
 define i32 @compare4(i32 %a, i32 %b) nounwind readnone {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = !cmp.eq(r{{[0-9]+}},r{{[0-9]+}})
 entry:
   %cmp = icmp ne i32 %a, %b
   %conv = zext i1 %cmp to i32

diff --git a/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll b/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll
index c97a736f10afc56ffc3a658c2bded3718f3a5832..9e6e465027f43e735eadc62081f11765ad838e32 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll
+++ b/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll
@@ -2,7 +2,7 @@
 ; Check that we generate compare to predicate register.
 
 define i32 @compare1(i32 %a, i32 %b) nounwind {
-; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
+; CHECK: p{{[0-3]}} = {{!?}}cmp.eq(r{{[0-9]+}},r{{[0-9]+}})
 entry:
   %cmp = icmp ne i32 %a, %b
   %add = add nsw i32 %a, %b
@@ -12,7 +12,7 @@ entry:
 }
 
 define i32 @compare2(i32 %a) nounwind {
-; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}#10)
+; CHECK: p{{[0-3]}} = {{!?}}cmp.eq(r{{[0-9]+}},#10)
 entry:
   %cmp = icmp ne i32 %a, 10
   %add = add nsw i32 %a, 10
@@ -22,7 +22,7 @@ entry:
 }
 
 define i32 @compare3(i32 %a, i32 %b) nounwind {
-; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
+; CHECK: p{{[0-3]}} = cmp.gt(r{{[0-9]+}},r{{[0-9]+}})
 entry:
   %cmp = icmp sgt i32 %a, %b
   %sub = sub nsw i32 %a, %b
@@ -32,7 +32,7 @@ entry:
 }
 
 define i32 @compare4(i32 %a) nounwind {
-; CHECK: p{{[0-3]}}{{ *}}={{ *}}cmp.gt(r{{[0-9]+}},{{ *}}#10)
+; CHECK: p{{[0-3]}} = cmp.gt(r{{[0-9]+}},#10)
 entry:
   %cmp = icmp sgt i32 %a, 10
   %sub = sub nsw i32 %a, 10

diff --git a/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll b/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
index 55edb22f46dcb0ec28427d594ca5d136b4e17a85..57783d421a404b42c0bf73077c6c4521742f3c2f 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
+++ b/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
@@ -6,7 +6,7 @@
 @foo = common global %struct.struc zeroinitializer, align 4
 
 define void @loadWord(i32 %val1, i32 %val2, i32* nocapture %ival) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##foo{{ *}}+{{ *}}4)
+; CHECK: r{{[0-9]+}} = memw(##foo+4)
 entry:
   %cmp = icmp sgt i32 %val1, %val2
   br i1 %cmp, label %if.then, label %if.end
@@ -21,7 +21,7 @@ if.end:                                           ; preds = %if.then, %entry
 }
 
 define void @loadByte(i32 %val1, i32 %val2, i8* nocapture %ival) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(##foo{{ *}}+{{ *}}1)
+; CHECK: r{{[0-9]+}} = memub(##foo+1)
 entry:
   %cmp = icmp sgt i32 %val1, %val2
   br i1 %cmp, label %if.then, label %if.end
@@ -36,7 +36,7 @@ if.end:                                           ; preds = %if.then, %entry
 }
 
 define void @loadHWord(i32 %val1, i32 %val2, i16* %ival) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(##foo{{ *}}+{{ *}}2)
+; CHECK: r{{[0-9]+}} = memuh(##foo+2)
 entry:
   %cmp = icmp sgt i32 %val1, %val2
   br i1 %cmp, label %if.then, label %if.end

diff --git a/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll b/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
index 6b181cabe4752770735d06e43ada3aa8010cafaa..66391b954d0ec4bc650a2af130961f741a925e78 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
+++ b/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
@@ -6,7 +6,7 @@
 @foo = common global %struct.struc zeroinitializer, align 4
 
 define void @storeByte(i32 %val1, i32 %val2, i8 zeroext %ival) nounwind {
-; CHECK: memb(##foo{{ *}}+{{ *}}1){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: memb(##foo+1) = r{{[0-9]+}}
 entry:
   %cmp = icmp sgt i32 %val1, %val2
   br i1 %cmp, label %if.then, label %if.end
@@ -20,7 +20,7 @@ if.end:                                           ; preds = %if.then, %entry
 }
 
 define void @storeHW(i32 %val1, i32 %val2, i16 signext %ival) nounwind {
-; CHECK: memh(##foo{{ *}}+{{ *}}2){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: memh(##foo+2) = r{{[0-9]+}}
 entry:
   %cmp = icmp sgt i32 %val1, %val2
   br i1 %cmp, label %if.then, label %if.end

diff --git a/llvm/test/CodeGen/Hexagon/gp-rel.ll b/llvm/test/CodeGen/Hexagon/gp-rel.ll
index 00f57797b6f1d314734d353ee757f0caa856fdbf..ef913134f7cb0bc00c2f96f7576f5ff487503d82 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/gp-rel.ll
+++ b/llvm/test/CodeGen/Hexagon/gp-rel.ll
@@ -7,9 +7,9 @@
 
 define i32 @foo(i32 %p) #0 {
 entry:
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#a)
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(gp+#b)
-; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} = memw(gp+#a)
+; CHECK: r{{[0-9]+}} = memw(gp+#b)
+; CHECK: if (p{{[0-3]}}) memw(##c) = r{{[0-9]+}}
   %0 = load i32, i32* @a, align 4
   %1 = load i32, i32* @b, align 4
   %add = add nsw i32 %1, %0

diff --git a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
index f1a9d38f1b1cebb91c9963c688792c597be78d0e..fc9fe8ac80faef11c15890c5b1076e5e05c1a941 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
@@ -4,7 +4,7 @@
 ; load word
 
 define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2)
 entry:
   %tmp = add i32 %n, %m
   %scevgep9 = getelementptr i32, i32* %a, i32 %tmp
@@ -15,7 +15,7 @@ entry:
 ; load unsigned half word
 
 define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
+; CHECK: r{{[0-9]+}} = memuh(r{{[0-9]+}}+r{{[0-9]+}}<<#1)
 entry:
   %tmp = add i32 %n, %m
   %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
@@ -26,7 +26,7 @@ entry:
 ; load signed half word
 
 define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
+; CHECK: r{{[0-9]+}} = memh(r{{[0-9]+}}+r{{[0-9]+}}<<#1)
 entry:
   %tmp = add i32 %n, %m
   %scevgep9 = getelementptr i16, i16* %a, i32 %tmp
@@ -38,7 +38,7 @@ entry:
 ; load unsigned byte
 
 define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0)
+; CHECK: r{{[0-9]+}} = memub(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
 entry:
   %tmp = add i32 %n, %m
   %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
@@ -49,7 +49,7 @@ entry:
 ; load signed byte
 
 define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind {
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0)
+; CHECK: r{{[0-9]+}} = memb(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
 entry:
   %tmp = add i32 %n, %m
   %scevgep9 = getelementptr i8, i8* %a, i32 %tmp
@@ -61,7 +61,7 @@ entry:
 ; load doubleword
 
 define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind {
-; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3)
+; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+r{{[0-9]+}}<<#3)
 entry:
   %tmp = add i32 %n, %m
   %scevgep9 = getelementptr i64, i64* %a, i32 %tmp

diff --git a/llvm/test/CodeGen/Hexagon/memops.ll b/llvm/test/CodeGen/Hexagon/memops.ll
index 011a4e50e5d8efd4016f367866e951b1fe76070a..c3b8b7bdf98b311c35909479685df804834f82f0 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/memops.ll
+++ b/llvm/test/CodeGen/Hexagon/memops.ll
@@ -4,7 +4,7 @@
 define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_add5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memb(r{{[0-9]+}}+#0) += #5
   %0 = load i8, i8* %p, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %conv, 5
@@ -16,7 +16,7 @@ entry:
 define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_add:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv = zext i8 %x to i32
   %0 = load i8, i8* %p, align 1
   %conv1 = zext i8 %0 to i32
@@ -29,7 +29,7 @@ entry:
 define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_sub:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv = zext i8 %x to i32
   %0 = load i8, i8* %p, align 1
   %conv1 = zext i8 %0 to i32
@@ -42,7 +42,7 @@ entry:
 define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_or:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %0 = load i8, i8* %p, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %p, align 1
@@ -52,7 +52,7 @@ entry:
 define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_and:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %0 = load i8, i8* %p, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %p, align 1
@@ -62,7 +62,7 @@ entry:
 define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_clrbit:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = clrbit(#5)
   %0 = load i8, i8* %p, align 1
   %conv = zext i8 %0 to i32
   %and = and i32 %conv, 223
@@ -74,7 +74,7 @@ entry:
 define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_setbit:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = setbit(#7)
   %0 = load i8, i8* %p, align 1
   %conv = zext i8 %0 to i32
   %or = or i32 %conv, 128
@@ -86,7 +86,7 @@ entry:
 define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_add5_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memb(r{{[0-9]+}}+#0) += #5
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
@@ -99,7 +99,7 @@ entry:
 define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_add_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
@@ -113,7 +113,7 @@ entry:
 define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_sub_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
@@ -127,7 +127,7 @@ entry:
 define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_or_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
@@ -138,7 +138,7 @@ entry:
 define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_and_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
@@ -149,7 +149,7 @@ entry:
 define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_clrbit_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = clrbit(#5)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
@@ -162,7 +162,7 @@ entry:
 define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_setbit_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = setbit(#7)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
@@ -175,7 +175,7 @@ entry:
 define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_add5_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
+; CHECK:  memb(r{{[0-9]+}}+#5) += #5
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
@@ -188,7 +188,7 @@ entry:
 define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_add_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) += r{{[0-9]+}}
   %conv = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
@@ -202,7 +202,7 @@ entry:
 define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_sub_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) -= r{{[0-9]+}}
   %conv = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
@@ -216,7 +216,7 @@ entry:
 define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_or_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
@@ -227,7 +227,7 @@ entry:
 define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_and_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
@@ -238,7 +238,7 @@ entry:
 define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_clrbit_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#5) = clrbit(#5)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
@@ -251,7 +251,7 @@ entry:
 define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_char_setbit_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#5) = setbit(#7)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
@@ -264,7 +264,7 @@ entry:
 define void @memop_signed_char_add5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_add5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memb(r{{[0-9]+}}+#0) += #5
   %0 = load i8, i8* %p, align 1
   %conv2 = zext i8 %0 to i32
   %add = add nsw i32 %conv2, 5
@@ -276,7 +276,7 @@ entry:
 define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_add:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
   %0 = load i8, i8* %p, align 1
   %conv13 = zext i8 %0 to i32
@@ -289,7 +289,7 @@ entry:
 define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_sub:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
   %0 = load i8, i8* %p, align 1
   %conv13 = zext i8 %0 to i32
@@ -302,7 +302,7 @@ entry:
 define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_or:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %0 = load i8, i8* %p, align 1
   %or3 = or i8 %0, %x
   store i8 %or3, i8* %p, align 1
@@ -312,7 +312,7 @@ entry:
 define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_and:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %0 = load i8, i8* %p, align 1
   %and3 = and i8 %0, %x
   store i8 %and3, i8* %p, align 1
@@ -322,7 +322,7 @@ entry:
 define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_clrbit:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = clrbit(#5)
   %0 = load i8, i8* %p, align 1
   %conv2 = zext i8 %0 to i32
   %and = and i32 %conv2, 223
@@ -334,7 +334,7 @@ entry:
 define void @memop_signed_char_setbit(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_setbit:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = setbit(#7)
   %0 = load i8, i8* %p, align 1
   %conv2 = zext i8 %0 to i32
   %or = or i32 %conv2, 128
@@ -346,7 +346,7 @@ entry:
 define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_add5_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memb(r{{[0-9]+}}+#0) += #5
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
@@ -359,7 +359,7 @@ entry:
 define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_add_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
@@ -373,7 +373,7 @@ entry:
 define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_sub_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
@@ -387,7 +387,7 @@ entry:
 define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_or_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
@@ -398,7 +398,7 @@ entry:
 define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_and_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
@@ -409,7 +409,7 @@ entry:
 define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_clrbit_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = clrbit(#5)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
@@ -422,7 +422,7 @@ entry:
 define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_setbit_index:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#0) = setbit(#7)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i
   %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
@@ -435,7 +435,7 @@ entry:
 define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_add5_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5
+; CHECK:  memb(r{{[0-9]+}}+#5) += #5
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
@@ -448,7 +448,7 @@ entry:
 define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_add_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) += r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
@@ -462,7 +462,7 @@ entry:
 define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_sub_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) -= r{{[0-9]+}}
   %conv4 = zext i8 %x to i32
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
@@ -476,7 +476,7 @@ entry:
 define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_or_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %or3 = or i8 %0, %x
@@ -487,7 +487,7 @@ entry:
 define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_and_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memb(r{{[0-9]+}}+#5) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %and3 = and i8 %0, %x
@@ -498,7 +498,7 @@ entry:
 define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_clrbit_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#5) = clrbit(#5)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
@@ -511,7 +511,7 @@ entry:
 define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_char_setbit_index5:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memb(r{{[0-9]+}}+#5) = setbit(#7)
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 5
   %0 = load i8, i8* %add.ptr, align 1
   %conv2 = zext i8 %0 to i32
@@ -524,7 +524,7 @@ entry:
 define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_add5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memh(r{{[0-9]+}}+#0) += #5
   %0 = load i16, i16* %p, align 2
   %conv = zext i16 %0 to i32
   %add = add nsw i32 %conv, 5
@@ -536,7 +536,7 @@ entry:
 define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_add:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv = zext i16 %x to i32
   %0 = load i16, i16* %p, align 2
   %conv1 = zext i16 %0 to i32
@@ -549,7 +549,7 @@ entry:
 define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_sub:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv = zext i16 %x to i32
   %0 = load i16, i16* %p, align 2
   %conv1 = zext i16 %0 to i32
@@ -562,7 +562,7 @@ entry:
 define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_or:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %0 = load i16, i16* %p, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %p, align 2
@@ -572,7 +572,7 @@ entry:
 define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_and:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %0 = load i16, i16* %p, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %p, align 2
@@ -582,7 +582,7 @@ entry:
 define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_clrbit:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = clrbit(#5)
   %0 = load i16, i16* %p, align 2
   %conv = zext i16 %0 to i32
   %and = and i32 %conv, 65503
@@ -594,7 +594,7 @@ entry:
 define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_setbit:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = setbit(#7)
   %0 = load i16, i16* %p, align 2
   %conv = zext i16 %0 to i32
   %or = or i32 %conv, 128
@@ -606,7 +606,7 @@ entry:
 define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_add5_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memh(r{{[0-9]+}}+#0) += #5
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
@@ -619,7 +619,7 @@ entry:
 define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_add_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
@@ -633,7 +633,7 @@ entry:
 define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_sub_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
@@ -647,7 +647,7 @@ entry:
 define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_or_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
@@ -658,7 +658,7 @@ entry:
 define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_and_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
@@ -669,7 +669,7 @@ entry:
 define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_clrbit_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = clrbit(#5)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
@@ -682,7 +682,7 @@ entry:
 define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_setbit_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = setbit(#7)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
@@ -695,7 +695,7 @@ entry:
 define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_add5_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
+; CHECK:  memh(r{{[0-9]+}}+#10) += #5
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
@@ -708,7 +708,7 @@ entry:
 define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_add_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) += r{{[0-9]+}}
   %conv = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
@@ -722,7 +722,7 @@ entry:
 define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_sub_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) -= r{{[0-9]+}}
   %conv = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
@@ -736,7 +736,7 @@ entry:
 define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_or_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
@@ -747,7 +747,7 @@ entry:
 define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_and_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
@@ -758,7 +758,7 @@ entry:
 define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_clrbit_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#10) = clrbit(#5)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
@@ -771,7 +771,7 @@ entry:
 define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_short_setbit_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#10) = setbit(#7)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %conv = zext i16 %0 to i32
@@ -784,7 +784,7 @@ entry:
 define void @memop_signed_short_add5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_add5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memh(r{{[0-9]+}}+#0) += #5
   %0 = load i16, i16* %p, align 2
   %conv2 = zext i16 %0 to i32
   %add = add nsw i32 %conv2, 5
@@ -796,7 +796,7 @@ entry:
 define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_add:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
   %0 = load i16, i16* %p, align 2
   %conv13 = zext i16 %0 to i32
@@ -809,7 +809,7 @@ entry:
 define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_sub:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
   %0 = load i16, i16* %p, align 2
   %conv13 = zext i16 %0 to i32
@@ -822,7 +822,7 @@ entry:
 define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_or:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %0 = load i16, i16* %p, align 2
   %or3 = or i16 %0, %x
   store i16 %or3, i16* %p, align 2
@@ -832,7 +832,7 @@ entry:
 define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_and:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %0 = load i16, i16* %p, align 2
   %and3 = and i16 %0, %x
   store i16 %and3, i16* %p, align 2
@@ -842,7 +842,7 @@ entry:
 define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_clrbit:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = clrbit(#5)
   %0 = load i16, i16* %p, align 2
   %conv2 = zext i16 %0 to i32
   %and = and i32 %conv2, 65503
@@ -854,7 +854,7 @@ entry:
 define void @memop_signed_short_setbit(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_setbit:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = setbit(#7)
   %0 = load i16, i16* %p, align 2
   %conv2 = zext i16 %0 to i32
   %or = or i32 %conv2, 128
@@ -866,7 +866,7 @@ entry:
 define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_add5_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memh(r{{[0-9]+}}+#0) += #5
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
@@ -879,7 +879,7 @@ entry:
 define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_add_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
@@ -893,7 +893,7 @@ entry:
 define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_sub_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
@@ -907,7 +907,7 @@ entry:
 define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_or_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
@@ -918,7 +918,7 @@ entry:
 define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_and_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
@@ -929,7 +929,7 @@ entry:
 define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_clrbit_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = clrbit(#5)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
@@ -942,7 +942,7 @@ entry:
 define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_setbit_index:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#0) = setbit(#7)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i
   %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
@@ -955,7 +955,7 @@ entry:
 define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_add5_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5
+; CHECK:  memh(r{{[0-9]+}}+#10) += #5
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
@@ -968,7 +968,7 @@ entry:
 define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_add_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) += r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
@@ -982,7 +982,7 @@ entry:
 define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_sub_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) -= r{{[0-9]+}}
   %conv4 = zext i16 %x to i32
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
@@ -996,7 +996,7 @@ entry:
 define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_or_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %or3 = or i16 %0, %x
@@ -1007,7 +1007,7 @@ entry:
 define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_and_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memh(r{{[0-9]+}}+#10) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %and3 = and i16 %0, %x
@@ -1018,7 +1018,7 @@ entry:
 define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_clrbit_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#10) = clrbit(#5)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
@@ -1031,7 +1031,7 @@ entry:
 define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_short_setbit_index5:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memh(r{{[0-9]+}}+#10) = setbit(#7)
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 5
   %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
@@ -1044,7 +1044,7 @@ entry:
 define void @memop_signed_int_add5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_add5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memw(r{{[0-9]+}}+#0) += #5
   %0 = load i32, i32* %p, align 4
   %add = add i32 %0, 5
   store i32 %add, i32* %p, align 4
@@ -1054,7 +1054,7 @@ entry:
 define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_add:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %add = add i32 %0, %x
   store i32 %add, i32* %p, align 4
@@ -1064,7 +1064,7 @@ entry:
 define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_sub:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %sub = sub i32 %0, %x
   store i32 %sub, i32* %p, align 4
@@ -1074,7 +1074,7 @@ entry:
 define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_or:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %p, align 4
@@ -1084,7 +1084,7 @@ entry:
 define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_and:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %p, align 4
@@ -1094,7 +1094,7 @@ entry:
 define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_clrbit:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = clrbit(#5)
   %0 = load i32, i32* %p, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %p, align 4
@@ -1104,7 +1104,7 @@ entry:
 define void @memop_signed_int_setbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_setbit:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = setbit(#7)
   %0 = load i32, i32* %p, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %p, align 4
@@ -1114,7 +1114,7 @@ entry:
 define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_add5_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memw(r{{[0-9]+}}+#0) += #5
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, 5
@@ -1125,7 +1125,7 @@ entry:
 define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_add_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, %x
@@ -1136,7 +1136,7 @@ entry:
 define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_sub_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %sub = sub i32 %0, %x
@@ -1147,7 +1147,7 @@ entry:
 define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_or_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
@@ -1158,7 +1158,7 @@ entry:
 define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_and_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
@@ -1169,7 +1169,7 @@ entry:
 define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_clrbit_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = clrbit(#5)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
@@ -1180,7 +1180,7 @@ entry:
 define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_setbit_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = setbit(#7)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128
@@ -1191,7 +1191,7 @@ entry:
 define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_add5_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
+; CHECK:  memw(r{{[0-9]+}}+#20) += #5
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, 5
@@ -1202,7 +1202,7 @@ entry:
 define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_add_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) += r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %add = add i32 %0, %x
@@ -1213,7 +1213,7 @@ entry:
 define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_sub_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) -= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %sub = sub i32 %0, %x
@@ -1224,7 +1224,7 @@ entry:
 define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_or_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
@@ -1235,7 +1235,7 @@ entry:
 define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_and_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
@@ -1246,7 +1246,7 @@ entry:
 define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_clrbit_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#20) = clrbit(#5)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
@@ -1257,7 +1257,7 @@ entry:
 define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_signed_int_setbit_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#20) = setbit(#7)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128
@@ -1268,7 +1268,7 @@ entry:
 define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_add5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memw(r{{[0-9]+}}+#0) += #5
   %0 = load i32, i32* %p, align 4
   %add = add nsw i32 %0, 5
   store i32 %add, i32* %p, align 4
@@ -1278,7 +1278,7 @@ entry:
 define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_add:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %add = add nsw i32 %0, %x
   store i32 %add, i32* %p, align 4
@@ -1288,7 +1288,7 @@ entry:
 define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_sub:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %sub = sub nsw i32 %0, %x
   store i32 %sub, i32* %p, align 4
@@ -1298,7 +1298,7 @@ entry:
 define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_or:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %or = or i32 %0, %x
   store i32 %or, i32* %p, align 4
@@ -1308,7 +1308,7 @@ entry:
 define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_and:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %0 = load i32, i32* %p, align 4
   %and = and i32 %0, %x
   store i32 %and, i32* %p, align 4
@@ -1318,7 +1318,7 @@ entry:
 define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_clrbit:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = clrbit(#5)
   %0 = load i32, i32* %p, align 4
   %and = and i32 %0, -33
   store i32 %and, i32* %p, align 4
@@ -1328,7 +1328,7 @@ entry:
 define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_setbit:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = setbit(#7)
   %0 = load i32, i32* %p, align 4
   %or = or i32 %0, 128
   store i32 %or, i32* %p, align 4
@@ -1338,7 +1338,7 @@ entry:
 define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_add5_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5
+; CHECK:  memw(r{{[0-9]+}}+#0) += #5
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, 5
@@ -1349,7 +1349,7 @@ entry:
 define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_add_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) += r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, %x
@@ -1360,7 +1360,7 @@ entry:
 define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_sub_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) -= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %sub = sub nsw i32 %0, %x
@@ -1371,7 +1371,7 @@ entry:
 define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_or_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
@@ -1382,7 +1382,7 @@ entry:
 define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_and_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#0) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
@@ -1393,7 +1393,7 @@ entry:
 define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_clrbit_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = clrbit(#5)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
@@ -1404,7 +1404,7 @@ entry:
 define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_setbit_index:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#0) = setbit(#7)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128
@@ -1415,7 +1415,7 @@ entry:
 define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_add5_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5
+; CHECK:  memw(r{{[0-9]+}}+#20) += #5
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, 5
@@ -1426,7 +1426,7 @@ entry:
 define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_add_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) += r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %add = add nsw i32 %0, %x
@@ -1437,7 +1437,7 @@ entry:
 define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_sub_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) -= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %sub = sub nsw i32 %0, %x
@@ -1448,7 +1448,7 @@ entry:
 define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_or_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) |= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, %x
@@ -1459,7 +1459,7 @@ entry:
 define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_and_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}}
+; CHECK:  memw(r{{[0-9]+}}+#20) &= r{{[0-9]+}}
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, %x
@@ -1470,7 +1470,7 @@ entry:
 define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_clrbit_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#20) = clrbit(#5)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %and = and i32 %0, -33
@@ -1481,7 +1481,7 @@ entry:
 define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind {
 entry:
 ; CHECK-LABEL: memop_unsigned_int_setbit_index5:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}})
+; CHECK:  memw(r{{[0-9]+}}+#20) = setbit(#7)
   %add.ptr = getelementptr inbounds i32, i32* %p, i32 5
   %0 = load i32, i32* %add.ptr, align 4
   %or = or i32 %0, 128

diff --git a/llvm/test/CodeGen/Hexagon/memops1.ll b/llvm/test/CodeGen/Hexagon/memops1.ll
index 37e885b6e0cb70e3b688838ef9c7a92520fa4a53..14204ef3d8010d7688c8281435848dd4a920caae 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/memops1.ll
+++ b/llvm/test/CodeGen/Hexagon/memops1.ll
@@ -4,7 +4,7 @@
 
 define void @f(i32* %p) nounwind {
 entry:
-; CHECK:  memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1
+; CHECK:  memw(r{{[0-9]+}}+#40) -= #1
   %p.addr = alloca i32*, align 4
   store i32* %p, i32** %p.addr, align 4
   %0 = load i32*, i32** %p.addr, align 4
@@ -17,7 +17,7 @@ entry:
 
 define void @g(i32* %p, i32 %i) nounwind {
 entry:
-; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1
+; CHECK: memw(r{{[0-9]+}}+#40) -= #1
   %p.addr = alloca i32*, align 4
   %i.addr = alloca i32, align 4
   store i32* %p, i32** %p.addr, align 4

diff --git a/llvm/test/CodeGen/Hexagon/memops2.ll b/llvm/test/CodeGen/Hexagon/memops2.ll
index f9f8a247811997a6641a62c57cde72645afb5306..e427dd1af9447f68a05274fd0cbce8e7debc1a6e 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/memops2.ll
+++ b/llvm/test/CodeGen/Hexagon/memops2.ll
@@ -4,7 +4,7 @@
 
 define void @f(i16* nocapture %p) nounwind {
 entry:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1
+; CHECK:  memh(r{{[0-9]+}}+#20) -= #1
   %add.ptr = getelementptr inbounds i16, i16* %p, i32 10
   %0 = load i16, i16* %add.ptr, align 2
   %conv2 = zext i16 %0 to i32
@@ -16,7 +16,7 @@ entry:
 
 define void @g(i16* nocapture %p, i32 %i) nounwind {
 entry:
-; CHECK:  memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1
+; CHECK:  memh(r{{[0-9]+}}+#20) -= #1
   %add.ptr.sum = add i32 %i, 10
   %add.ptr1 = getelementptr inbounds i16, i16* %p, i32 %add.ptr.sum
   %0 = load i16, i16* %add.ptr1, align 2

diff --git a/llvm/test/CodeGen/Hexagon/memops3.ll b/llvm/test/CodeGen/Hexagon/memops3.ll
index 6cd7fdc48617ee872ed6465c6fccbc2dd4c008c5..606be7096e27d47534438a505a31d8444c1d62f0 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/memops3.ll
+++ b/llvm/test/CodeGen/Hexagon/memops3.ll
@@ -4,7 +4,7 @@
 
 define void @f(i8* nocapture %p) nounwind {
 entry:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1
+; CHECK:  memb(r{{[0-9]+}}+#10) -= #1
   %add.ptr = getelementptr inbounds i8, i8* %p, i32 10
   %0 = load i8, i8* %add.ptr, align 1
   %conv = zext i8 %0 to i32
@@ -16,7 +16,7 @@ entry:
 
 define void @g(i8* nocapture %p, i32 %i) nounwind {
 entry:
-; CHECK:  memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1
+; CHECK:  memb(r{{[0-9]+}}+#10) -= #1
   %add.ptr.sum = add i32 %i, 10
   %add.ptr1 = getelementptr inbounds i8, i8* %p, i32 %add.ptr.sum
   %0 = load i8, i8* %add.ptr1, align 1

diff --git a/llvm/test/CodeGen/Hexagon/multi-cycle.ll b/llvm/test/CodeGen/Hexagon/multi-cycle.ll
index b8caef90397d4ecc84c3417dfdc9be420ef8bbd8..920ca9fddb4a33ded5c989b5efe7be585965ffd6 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/multi-cycle.ll
+++ b/llvm/test/CodeGen/Hexagon/multi-cycle.ll
@@ -1,12 +1,12 @@
 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
 
-; CHECK: v{{[0-9]+}}.h{{ *}}={{ *}}vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
+; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
 ; CHECK: }
 ; CHECK: {
-; CHECK: v{{[0-9]+}}{{ *}}={{ *}}valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
+; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
 ; CHECK: }
 ; CHECK: {
-; CHECK: v{{[0-9]+}}{{ *}}={{ *}}valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
+; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
 
 target triple = "hexagon"
 

diff --git a/llvm/test/CodeGen/Hexagon/pic-jumptables.ll b/llvm/test/CodeGen/Hexagon/pic-jumptables.ll
index 271105cb4b5bdaf285a60a12687bdffb0c0d0e18..caf3f9cb81fe5148d0e1a077ae18d639224195c5 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/pic-jumptables.ll
+++ b/llvm/test/CodeGen/Hexagon/pic-jumptables.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
 
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add({{pc|PC}}{{ *}},{{ *}}##
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = add({{pc|PC}},##
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2)
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},r{{[0-9]+}})
 
 
 define i32 @test(i32 %y) nounwind {

diff --git a/llvm/test/CodeGen/Hexagon/pic-regusage.ll b/llvm/test/CodeGen/Hexagon/pic-regusage.ll
index 53c4ba40cb9a4143b2eb19d5762cb74a2f107c7d..e6cf1cfa6e470e5bab32844ad7cf7842d0a7d550 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/pic-regusage.ll
+++ b/llvm/test/CodeGen/Hexagon/pic-regusage.ll
@@ -5,7 +5,7 @@
 ; R14, R15 and R28).
 ; CHECK: call __save_r16_through_r27
 ; CHECK: }
-; CHECK: r14{{ *}}=
+; CHECK: r14 =
 
 @.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
 
@@ -29,7 +29,7 @@ declare i32 @printf(i8*, ...) #0
 ; Same as above for R15.
 ; CHECK: call __save_r16_through_r27
 ; CHECK: }
-; CHECK: r15{{ *}}=
+; CHECK: r15 =
 
 ; Function Attrs: nounwind optsize
 define i32 @_Z7testR15Pi(i32* nocapture %res) #0 {
@@ -48,7 +48,7 @@ entry:
 ; Same as above for R28.
 ; CHECK: call __save_r16_through_r27
 ; CHECK: }
-; CHECK: r28{{ *}}=
+; CHECK: r28 =
 
 ; Function Attrs: nounwind optsize
 define i32 @_Z7testR28Pi(i32* nocapture %res) #0 {

diff --git a/llvm/test/CodeGen/Hexagon/postinc-load.ll b/llvm/test/CodeGen/Hexagon/postinc-load.ll
index a9d987981d652371bcb86cc25c406e8a9ae9ca9f..8d8c93d76bf95b36e1251753fe85627e26a2cead 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/postinc-load.ll
+++ b/llvm/test/CodeGen/Hexagon/postinc-load.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
 
 ; Check that post-increment load instructions are being generated.
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}++{{ *}}#4{{ *}})
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}++#4)
 
 define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {
 entry:

diff --git a/llvm/test/CodeGen/Hexagon/postinc-offset.ll b/llvm/test/CodeGen/Hexagon/postinc-offset.ll
index cf8c4e5f71d253d43526410c6dc983d09c352419..3b28001c2f3ac0b66ff57428ebee5c8feaf370a5 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/postinc-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/postinc-offset.ll
@@ -2,8 +2,8 @@
 ; RUN:      < %s | FileCheck %s
 
 ; CHECK: {
-; CHECK: ={{ *}}memd([[REG0:(r[0-9]+)]]{{ *}}++{{ *}}#8)
-; CHECK-NOT: memw([[REG0]]{{ *}}+{{ *}}#0){{ *}}=
+; CHECK: = memd([[REG0:(r[0-9]+)]]++#8)
+; CHECK-NOT: memw([[REG0]]+#0) =
 ; CHECK: }
 
 define void @main() #0 {

diff --git a/llvm/test/CodeGen/Hexagon/postinc-store.ll b/llvm/test/CodeGen/Hexagon/postinc-store.ll
index 6315ca14a952e0802c017ebc51e56ecc3854bc1d..276a7d8e0ff184d337ea320a97a6dea254319e5b 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/postinc-store.ll
+++ b/llvm/test/CodeGen/Hexagon/postinc-store.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
 
 ; Check that post-increment store instructions are being generated.
-; CHECK: memw(r{{[0-9]+}}{{ *}}++{{ *}}#4{{ *}}){{ *}}={{ *}}r{{[0-9]+}}
+; CHECK: memw(r{{[0-9]+}}++#4) = r{{[0-9]+}}
 
 define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {
 entry:

diff --git a/llvm/test/CodeGen/Hexagon/pred-gp.ll b/llvm/test/CodeGen/Hexagon/pred-gp.ll
index 3868e098007ff52030c01734b4f826d08a5a28d0..76a621699b627719c82a13690c645bd6d6243f8e 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/pred-gp.ll
+++ b/llvm/test/CodeGen/Hexagon/pred-gp.ll
@@ -7,8 +7,8 @@
 
 ; Function Attrs: nounwind
 define i32 @test2(i8 zeroext %a, i8 zeroext %b) #0 {
-; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}})
-; CHECK: if{{ *}}({{!*}}p{{[0-3]+}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}memw(##{{[cd]}})
+; CHECK: if ({{!?}}p{{[0-3]+}}{{(.new)?}}) r{{[0-9]+}} = memw(##{{[cd]}})
+; CHECK: if ({{!?}}p{{[0-3]+}}) r{{[0-9]+}} = memw(##{{[cd]}})
 entry:
   %cmp = icmp eq i8 %a, %b
   br i1 %cmp, label %if.then, label %entry.if.end_crit_edge

diff --git a/llvm/test/CodeGen/Hexagon/pred-instrs.ll b/llvm/test/CodeGen/Hexagon/pred-instrs.ll
index e0a75f13dfa85d9382df2747f3515a90f63fb1a2..da8ace98a0b2d69171ab251ee4ef94dbd122a396 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/pred-instrs.ll
+++ b/llvm/test/CodeGen/Hexagon/pred-instrs.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
 ; Check that we are able to predicate instructions.
 
-; CHECK: if{{ *}}({{!*}}p{{[0-3]}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}{{and|aslh}}
-; CHECK: if{{ *}}({{!*}}p{{[0-3]}}{{[.new]*}}){{ *}}r{{[0-9]+}}{{ *}}={{ *}}{{and|aslh}}
+; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
+; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
 @a = external global i32
 @d = external global i32
 

diff --git a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
index 40b4a819ad6159e73585ffcef208fa430e7ead3f..a0112a0988f61aa86f5fb7173a23d206f2c0f8d8 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
+++ b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll
@@ -3,7 +3,7 @@
 ; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}}
 ; CHECK: call puts
 ; CHECK: call print_vecpred
-; CHECK: v{{[0-9]+}}{{ *}}={{ *}}vmem(r{{[0-9]+}}+#3)
+; CHECK: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#3)
 
 target triple = "hexagon"
 

diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll b/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll
index fd75bbd58e367ed6d8b196b35f02f33cfaf224e6..01c493567372bd069f5d6059aed91c9b17a061fa 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll
@@ -23,7 +23,7 @@ polly.loop_header:                                ; preds = %polly.loop_after45,
   br i1 %0, label %polly.loop_body, label %do.cond
 
 polly.loop_body:                                  ; preds = %polly.loop_header
-  %p_25 = call i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32 undef)
+  %p_25 = call i32 @llvm.hexagon.A2.asrh(i32 undef)
   %1 = insertelement <4 x i32> undef, i32 %p_25, i32 3
   %2 = trunc <4 x i32> %1 to <4 x i16>
   store <4 x i16> %2, <4 x i16>* undef, align 8
@@ -39,4 +39,4 @@ polly.loop_body44:                                ; preds = %polly.loop_header43
   br label %polly.loop_header43
 }
 
-declare i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32) nounwind readnone
+declare i32 @llvm.hexagon.A2.asrh(i32) nounwind readnone