resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
- phys = <&pcie0_lane>;
+ phys = <&pcie_lane>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
status = "disabled";
};
- pcie0_phy: phy@1c07000 {
+ pcie_phy: phy@1c07000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
reg = <0x01c07000 0x1c4>;
#address-cells = <1>;
status = "disabled";
- pcie0_lane: lanes@1c06000 {
+ pcie_lane: lanes@1c06000 {
reg = <0x01c06000 0x104>, /* tx0 */
<0x01c06200 0x328>, /* rx0 */
<0x01c07200 0x1e8>, /* pcs */