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agx: Fix 32-bit bitwise shifts
author
Alyssa Rosenzweig
<alyssa@rosenzweig.io>
Sun, 4 Jul 2021 22:44:34 +0000
(18:44 -0400)
committer
Marge Bot
<eric+marge@anholt.net>
Mon, 5 Jul 2021 20:56:04 +0000
(20:56 +0000)
Fixes dEQP-GLES2.functional.shaders.functions.qualifiers.const_int_fragment
Fixes:
e50bae00f48
("agx: Add 32-bit bitwise shifts")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
src/asahi/compiler/agx_compile.c
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diff --git
a/src/asahi/compiler/agx_compile.c
b/src/asahi/compiler/agx_compile.c
index
ef568e6
..
2792197
100644
(file)
--- a/
src/asahi/compiler/agx_compile.c
+++ b/
src/asahi/compiler/agx_compile.c
@@
-536,7
+536,7
@@
agx_emit_alu(agx_builder *b, nir_alu_instr *instr)
case nir_op_ineg: return agx_iadd_to(b, dst, agx_zero(), agx_neg(s0), 0);
case nir_op_imul: return agx_imad_to(b, dst, s0, s1, agx_zero(), 0);
- case nir_op_ishl: return agx_bfi_to(b, dst,
s0, agx_zero()
, s1, 0);
+ case nir_op_ishl: return agx_bfi_to(b, dst,
agx_zero(), s0
, s1, 0);
case nir_op_ushr: return agx_bfeil_to(b, dst, agx_zero(), s0, s1, 0);
case nir_op_ishr: return agx_asr_to(b, dst, s0, s1);