#define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
#define LTQ_WDT_SR 0x8 /* watchdog status register */
#define LTQ_WDT_SR_EN BIT(31) /* Enable */
+#define LTQ_WDT_SR_VALUE_MASK GENMASK(15, 0) /* Timer value */
#define LTQ_WDT_DIVIDER 0x40000
return 0;
}
+static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
+{
+ struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
+ u64 timeout;
+
+ timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
+ return do_div(timeout, priv->clk_rate);
+}
+
static const struct watchdog_ops ltq_wdt_ops = {
.owner = THIS_MODULE,
.start = ltq_wdt_start,
.stop = ltq_wdt_stop,
.ping = ltq_wdt_ping,
+ .get_timeleft = ltq_wdt_get_timeleft,
};
static int ltq_wdt_xrx_bootstatus_get(struct device *dev)