F: board/efi/efi-x86_app
F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
+F: drivers/block/efi-media-uclass.c
+F: drivers/block/sb_efi_media.c
F: lib/efi/efi_app.c
F: scripts/build-efi.sh
+F: test/dm/efi_media.c
EFI PAYLOAD
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
VERSION = 2022
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb \
- px30-px30-core-ctouch2.dtb \
- px30-px30-core-edimm2.2.dtb \
+ px30-engicam-px30-core-ctouch2.dtb \
+ px30-engicam-px30-core-ctouch2-of10.dtb \
+ px30-engicam-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
compatible = "audio-graph-card";
label = "rcar-sound";
dais = <&rsnd_port0>, <&rsnd_port1>;
+ widgets = "Microphone", "Mic Jack",
+ "Line", "Line In Jack",
+ "Headphone", "Headphone Jack";
+ mic-det-gpio = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ routing = "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN3R", "MICBIAS",
+ "Mic Jack", "IN3R";
};
vccq_sdhi0: regulator-vccq-sdhi0 {
&ehci0 {
dr_mode = "otg";
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&ehci1 {
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&hdmi0 {
};
&rcar_sound {
- pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
- playback = <&ssi1 &dvc1 &src1>;
+ playback = <&ssi1>, <&dvc1>, <&src1>;
capture = <&ssi0>;
};
};
#include <dt-bindings/clk/versaclock.h>
/ {
- aliases {
- spi0 = &rpc;
- };
-
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0xc000000>;
- };
-
- memory@57000000 {
- device_type = "memory";
- reg = <0x0 0x57000000 0x0 0x29000000>;
+ reg = <0x0 0x48000000 0x0 0x78000000>;
};
osc_32k: osc_32k {
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
+ phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
+ clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
+ clock-names = "fck", "refclk";
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id004d.d074",
+ "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
eeprom@50 {
- compatible = "microchip,at24c64", "atmel,24c64";
+ compatible = "microchip,24c64", "atmel,24c64";
pagesize = <32>;
read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x50>;
};
};
-&rpc {
- compatible = "renesas,rcar-gen3-rpc";
- num-cs = <1>;
- spi-max-frequency = <40000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- flash0: spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "spi-flash", "jedec,spi-nor";
- spi-max-frequency = <40000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <1>;
- };
-};
-
&scif_clk {
clock-frequency = <14745600>;
};
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
&usb2_clksel {
- status = "okay";
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
- <&versaclock5 3>, <&usb3s0_clk>;
- clock-names = "ehci_ohci", "hs-usb-if",
- "usb_extal", "usb_xtal";
+ <&versaclock5 3>, <&usb3s0_clk>;
+ status = "okay";
};
&usb3s0_clk {
*/
/ {
+ aliases {
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ };
+
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys"; /* +5V */
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&xin32k>;
+ clock-names = "ext_clock";
+ post-power-on-delay-ms = <80>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ };
+
+ vcc3v3_btreg: vcc3v3-btreg {
+ compatible = "regulator-gpio";
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable_h>;
+ regulator-name = "btreg-gpio-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ states = <3300000 0x0>;
+ };
+
+ vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_rf_aux_mod";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ sd-uhs-sdr104;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
};
&gmac {
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
&sdmmc {
cap-sd-highspeed;
card-detect-delay = <800>;
status = "okay";
};
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
&uart2 {
pinctrl-0 = <&uart2m1_xfer>;
status = "okay";
};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
*/
#include "px30-engicam-common.dtsi"
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+};
*/
#include "px30-engicam-common.dtsi"
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ panel {
+ compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+ backlight = <&backlight>;
+ data-mapping = "vesa-24";
+ power-supply = <&vcc3v3_lcd>;
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+/* LVDS_B(secondary) */
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
+ compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
+ "rockchip,px30";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ panel {
+ compatible = "ampire,am-1280800n3tzqw-t00h";
+ backlight = <&backlight>;
+ power-supply = <&vcc3v3_lcd>;
+ data-mapping = "vesa-24";
+
+ port {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+ };
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
/dts-v1/;
#include "px30.dtsi"
#include "px30-engicam-ctouch2.dtsi"
-#include "px30-px30-core.dtsi"
+#include "px30-engicam-px30-core.dtsi"
/ {
model = "Engicam PX30.Core C.TOUCH 2.0";
- compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
+ compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
"rockchip,px30";
chosen {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-edimm2.2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+ model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
+ "rockchip,px30";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdio_pwrseq {
+ reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+ enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+};
#include <dt-bindings/pinctrl/rockchip.h>
/ {
- compatible = "engicam,px30-px30-core", "rockchip,px30";
+ compatible = "engicam,px30-core", "rockchip,px30";
+
+ aliases {
+ mmc0 = &emmc;
+ };
};
&cpu0 {
};
};
+ vcc3v3_lcd: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc3v3_lcd";
+ };
+
vcc5v0_host: SWITCH_REG2 {
regulator-name = "vcc5v0_host";
regulator-always-on;
model = "Rockchip PX30 EVB";
compatible = "rockchip,px30-evb", "rockchip,px30";
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdio;
+ mmc2 = &emmc;
+ };
+
chosen {
- stdout-path = "serial2:115200n8";
+ stdout-path = "serial5:115200n8";
};
adc-keys {
cpu-supply = <&vdd_arm>;
};
+&csi_dphy {
+ status = "okay";
+};
+
&display_subsystem {
status = "okay";
};
};
panel@0 {
- compatible = "sitronix,st7703";
+ compatible = "xinpeng,xpp055c272";
reg = <0>;
backlight = <&backlight>;
iovcc-supply = <&vcc_1v8>;
vci-supply = <&vcc3v3_lcd>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mipi_in_panel: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
};
};
};
};
&emmc {
- bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_log>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
};
+&i2c1 {
+ status = "okay";
+
+ sensor@d {
+ compatible = "asahi-kasei,ak8963";
+ reg = <0x0d>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&vcc3v0_pmu>;
+ mount-matrix = "1", /* x0 */
+ "0", /* y0 */
+ "0", /* z0 */
+ "0", /* x1 */
+ "1", /* y1 */
+ "0", /* z1 */
+ "0", /* x2 */
+ "0", /* y2 */
+ "1"; /* z2 */
+ };
+
+ touchscreen@14 {
+ compatible = "goodix,gt1151";
+ reg = <0x14>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ VDDIO-supply = <&vcc3v3_lcd>;
+ };
+
+ sensor@4c {
+ compatible = "fsl,mma7660";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ /* These are relatively safe rise/fall times; TODO: measure */
+ i2c-scl-falling-time-ns = <50>;
+ i2c-scl-rising-time-ns = <300>;
+
+ ov5695: ov5695@36 {
+ compatible = "ovti,ov5695";
+ reg = <0x36>;
+ avdd-supply = <&vcc2v8_dvp>;
+ clocks = <&cru SCLK_CIF_OUT>;
+ clock-names = "xvclk";
+ dvdd-supply = <&vcc1v5_dvp>;
+ dovdd-supply = <&vcc1v8_dvp>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cif_clkout_m0>;
+ reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+
+ port {
+ ucam_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
&i2s1_2ch {
status = "okay";
};
vccio6-supply = <&vccio_flash>;
};
+&isp {
+ status = "okay";
+
+ ports {
+ port@0 {
+ mipi_in_ucam: endpoint@0 {
+ reg = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&ucam_out>;
+ };
+ };
+ };
+};
+
+&isp_mmu {
+ status = "okay";
+};
+
&pinctrl {
headphone {
hp_det: hp-det {
};
&sdmmc {
- bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <800>;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
+ status = "okay";
};
&sdio {
- bus-width = <4>;
cap-sd-highspeed;
keep-power-in-suspend;
non-removable;
status = "okay";
};
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer &uart1_cts>;
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
-&uart2 {
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-edimm2.2.dtsi"
-#include "px30-px30-core.dtsi"
-
-/ {
- model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
- compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
- "rockchip,px30";
-
- chosen {
- stdout-path = "serial2:115200n8";
- };
-};
u-boot,spl-boot-order = &emmc, &sdmmc;
};
+ dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,px30-dmc", "syscon";
+ reg = <0x0 0xff2a0000 0x0 0x1000>;
+ };
+
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
};
};
-&dmc {
- u-boot,dm-pre-reloc;
-};
-
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
&cru {
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
};
&pmucru {
u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
};
&saradc {
};
};
- cpu0_opp_table: cpu0-opp-table {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
};
arm-pmu {
- compatible = "arm,cortex-a53-pmu";
+ compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
- dmc: dmc {
- compatible = "rockchip,px30-dmc", "syscon";
- reg = <0x0 0xff2a0000 0x0 0x1000>;
- };
-
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopb_out>, <&vopl_out>;
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+ #power-domain-cells = <0>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>,
<&cru SCLK_MAC_REF>,
<&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
+ #power-domain-cells = <0>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+ #power-domain-cells = <0>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>,
<&cru SCLK_VOPB_PWM>;
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>;
+ #power-domain-cells = <0>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>,
pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
<&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>;
+ #power-domain-cells = <0>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
};
wdt: watchdog@ff1e0000 {
- compatible = "snps,dw-wdt";
+ compatible = "rockchip,px30-wdt", "snps,dw-wdt";
reg = <0x0 0xff1e0000 0x0 0x100>;
clocks = <&cru PCLK_WDT_NS>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "timer";
};
- amba {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- dmac: dmac@ff240000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff240000 0x0 0x4000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- };
+ dmac: dmac@ff240000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff240000 0x0 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
};
tsadc: tsadc@ff280000 {
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <120000>;
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&tsadc_otp_gpio>;
+ pinctrl-0 = <&tsadc_otp_pin>;
pinctrl-1 = <&tsadc_otp_out>;
- pinctrl-2 = <&tsadc_otp_gpio>;
+ pinctrl-2 = <&tsadc_otp_pin>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <200000000>;
};
pmucru: clock-controller@ff2bc000 {
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ assigned-clocks =
+ <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
+ <&pmucru SCLK_WIFI_PMU>;
+ assigned-clock-rates =
+ <1200000000>, <100000000>,
+ <26000000>;
};
usb2phy_grf: syscon@ff2c0000 {
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,px30-usb2phy";
reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
status = "disabled";
};
+ csi_dphy: phy@ff2f0000 {
+ compatible = "rockchip,px30-csi-dphy";
+ reg = <0x0 0xff2f0000 0x0 0x4000>;
+ clocks = <&cru PCLK_MIPICSIPHY>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ power-domains = <&power PX30_PD_VI>;
+ resets = <&cru SRST_MIPICSIPHY_P>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
usb20_otg: usb@ff300000 {
compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
"snps,dwc2";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
power-domains = <&power PX30_PD_USB>;
reg = <0x0 0xff340000 0x0 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
- clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
reg = <0x0 0xff350000 0x0 0x10000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>;
- clock-names = "usbhost";
phys = <&u2phy_host>;
phy-names = "usb";
power-domains = <&power PX30_PD_USB>;
status = "disabled";
};
- sdmmc: dwmmc@ff370000 {
+ sdmmc: mmc@ff370000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff370000 0x0 0x4000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
status = "disabled";
};
- sdio: dwmmc@ff380000 {
+ sdio: mmc@ff380000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff380000 0x0 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
status = "disabled";
};
- emmc: dwmmc@ff390000 {
+ emmc: mmc@ff390000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff390000 0x0 0x4000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <8>;
fifo-depth = <0x100>;
max-frequency = <150000000>;
pinctrl-names = "default";
status = "disabled";
};
- sfc: sfc@ff3a0000 {
+ sfc: spi@ff3a0000 {
compatible = "rockchip,sfc";
reg = <0x0 0xff3a0000 0x0 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
- pinctrl-names = "default";
pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+ pinctrl-names = "default";
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
+ nfc: nand-controller@ff3b0000 {
+ compatible = "rockchip,px30-nfc";
+ reg = <0x0 0xff3b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&cru SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
+ &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
gpu: gpu@ff400000 {
compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
clocks = <&cru SCLK_GPU>;
#cooling-cells = <2>;
power-domains = <&power PX30_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};
+ vpu: video-codec@ff442000 {
+ compatible = "rockchip,px30-vpu";
+ reg = <0x0 0xff442000 0x0 0x800>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@ff442800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff442800 0x0 0x100>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power PX30_PD_VPU>;
+ };
+
dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
power-domains = <&power PX30_PD_VO>;
- rockchip,grf = <&grf>;
status = "disabled";
vopb_out: port {
compatible = "rockchip,iommu";
reg = <0x0 0xff460f00 0x0 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vopl_mmu>;
power-domains = <&power PX30_PD_VO>;
- rockchip,grf = <&grf>;
status = "disabled";
vopl_out: port {
vopl_mmu: iommu@ff470f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff470f00 0x0 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
status = "disabled";
};
+ isp: isp@ff4a0000 {
+ compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
+ reg = <0x0 0xff4a0000 0x0 0x8000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp", "mi", "mipi";
+ clocks = <&cru SCLK_ISP>,
+ <&cru ACLK_ISP>,
+ <&cru HCLK_ISP>,
+ <&cru PCLK_ISP>;
+ clock-names = "isp", "aclk", "hclk", "pclk";
+ iommus = <&isp_mmu>;
+ phys = <&csi_dphy>;
+ phy-names = "dphy";
+ power-domains = <&power PX30_PD_VI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ isp_mmu: iommu@ff4a8000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff4a8000 0x0 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power PX30_PD_VI>;
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ };
+
qos_gmac: qos@ff518000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff518000 0x0 0x20>;
};
qos_gpu: qos@ff520000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff520000 0x0 0x20>;
};
qos_sdmmc: qos@ff52c000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff52c000 0x0 0x20>;
};
qos_emmc: qos@ff538000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538000 0x0 0x20>;
};
qos_nand: qos@ff538080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538080 0x0 0x20>;
};
qos_sdio: qos@ff538100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538100 0x0 0x20>;
};
qos_sfc: qos@ff538180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff538180 0x0 0x20>;
};
qos_usb_host: qos@ff540000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff540000 0x0 0x20>;
};
qos_usb_otg: qos@ff540080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff540080 0x0 0x20>;
};
qos_isp_128: qos@ff548000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548000 0x0 0x20>;
};
qos_isp_rd: qos@ff548080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548080 0x0 0x20>;
};
qos_isp_wr: qos@ff548100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548100 0x0 0x20>;
};
qos_isp_m1: qos@ff548180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548180 0x0 0x20>;
};
qos_vip: qos@ff548200 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff548200 0x0 0x20>;
};
qos_rga_rd: qos@ff550000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550000 0x0 0x20>;
};
qos_rga_wr: qos@ff550080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550080 0x0 0x20>;
};
qos_vop_m0: qos@ff550100 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550100 0x0 0x20>;
};
qos_vop_m1: qos@ff550180 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff550180 0x0 0x20>;
};
qos_vpu: qos@ff558000 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff558000 0x0 0x20>;
};
qos_vpu_r128: qos@ff558080 {
- compatible = "syscon";
+ compatible = "rockchip,px30-qos", "syscon";
reg = <0x0 0xff558080 0x0 0x20>;
};
#size-cells = <2>;
ranges;
- gpio0: gpio0@ff040000 {
+ gpio0: gpio@ff040000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff040000 0x0 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
- gpio1: gpio1@ff250000 {
+ gpio1: gpio@ff250000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff250000 0x0 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
- gpio2: gpio2@ff260000 {
+ gpio2: gpio@ff260000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
- gpio3: gpio3@ff270000 {
+ gpio3: gpio@ff270000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff270000 0x0 0x100>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
};
tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
+ tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
- serial_flash {
+ sfc {
sfc_bus4: sfc-bus4 {
rockchip,pins =
<1 RK_PA0 3 &pcfg_pull_none>,
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
*/
-/ {
- soc {
- u-boot,dm-pre-reloc;
- };
-};
-
-&cpg {
- u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
- u-boot,dm-pre-reloc;
-};
-
-&prr {
- u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
- u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
- /delete-property/ cd-gpios;
-};
-
-&sdhi2 {
- status = "disabled";
-};
+#include "rz-g2-beacon-u-boot.dtsi"
serial4 = &hscif2;
serial5 = &scif5;
ethernet0 = &avb;
+ mmc0 = &sdhi3;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi2;
};
chosen {
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
*/
-/ {
- soc {
- u-boot,dm-pre-reloc;
- };
-};
-
-&cpg {
- u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
- u-boot,dm-pre-reloc;
-};
-
-&prr {
- u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
- u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
- /delete-property/ cd-gpios;
-};
-
-&sdhi2 {
- status = "disabled";
-};
+#include "rz-g2-beacon-u-boot.dtsi"
serial5 = &scif5;
serial6 = &scif4;
ethernet0 = &avb;
+ mmc0 = &sdhi3;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi2;
};
chosen {
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
*/
-/ {
- soc {
- u-boot,dm-pre-reloc;
- };
-};
-
-&cpg {
- u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
- u-boot,dm-pre-reloc;
-};
-
-&prr {
- u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
- u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
- /delete-property/ cd-gpios;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr104;
- max-frequency = <208000000>;
-};
-
-&sdhi2 {
- status = "disabled";
-};
-
-&sdhi3 {
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
-};
+#include "rz-g2-beacon-u-boot.dtsi"
serial5 = &scif5;
serial6 = &scif4;
ethernet0 = &avb;
+ mmc0 = &sdhi3;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi2;
};
chosen {
serial2 = &uart2;
spi0 = &sfc;
};
+
+ dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,px30-dmc", "syscon";
+ reg = <0x0 0xff2a0000 0x0 0x1000>;
+ };
+
+ rng: rng@ff0b0000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff0b0000 0x0 0x4000>;
+ status = "okay";
+ };
};
/* U-Boot clk driver for px30 cannot set GPU_CLK */
<100000000>, <17000000>;
};
-&dmc {
- u-boot,dm-pre-reloc;
-};
-
&gpio0 {
u-boot,dm-pre-reloc;
};
u-boot,dm-pre-reloc;
};
-&{/sfc@ff3a0000/flash@0} {
+&{/spi@ff3a0000/flash@0} {
u-boot,dm-pre-reloc;
};
model = "ODROID-GO Advance";
compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
- chosen {
- stdout-path = "serial2:115200n8";
+ aliases {
+ mmc0 = &sdmmc;
};
- backlight: backlight {
- compatible = "pwm-backlight";
- power-supply = <&vcc_bl>;
- pwms = <&pwm1 0 25000 0>;
+ chosen {
+ stdout-path = "serial2:115200n8";
};
adc-joystick {
axis@0 {
reg = <0>;
- abs-range = <172 772>;
- abs-fuzz = <10>;
abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <172 772>;
linux,code = <ABS_X>;
};
axis@1 {
reg = <1>;
- abs-range = <278 815>;
- abs-fuzz = <10>;
abs-flat = <10>;
+ abs-fuzz = <10>;
+ abs-range = <278 815>;
linux,code = <ABS_Y>;
};
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_bl>;
+ pwms = <&pwm1 0 25000 0>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
rk817-sound {
compatible = "simple-audio-card";
+ simple-audio-card,name = "Analog";
simple-audio-card,format = "i2s";
- simple-audio-card,name = "rockchip,rk817-codec";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
- "Headphone", "Headphone Jack";
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
simple-audio-card,routing =
- "MIC_IN", "Mic Jack",
- "Headphone Jack", "HPOL",
- "Headphone Jack", "HPOR";
- simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
- simple-audio-card,codec-hp-det = <1>;
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
- simple-audio-card,cpu {
- sound-dai = <&i2s1_2ch>;
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
};
- simple-audio-card,codec {
- sound-dai = <&rk817_codec>;
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
};
};
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
- vin-supply = <&vccsys>;
+ regulator-boot-on;
+ vin-supply = <&usb_midu>;
};
};
backlight = <&backlight>;
iovcc-supply = <&vcc_lcd>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
vdd-supply = <&vcc_lcd>;
port {
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default", "pmic-sleep",
- "pmic-power-off", "pmic-reset";
- pinctrl-0 = <&pmic_int>;
- pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
- pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
- pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
- rockchip,system-power-controller;
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S1_OUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
wakeup-source;
#clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "xin32k";
+ #sound-dai-cells = <0>;
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vccsys>;
-
- pinctrl_rk8xx: pinctrl_rk8xx {
- gpio-controller;
- #gpio-cells = <2>;
-
- rk817_ts_gpio1: rk817_ts_gpio1 {
- pins = "gpio_ts";
- function = "pin_fun1";
- /* output-low; */
- /* input-enable; */
- };
-
- rk817_gt_gpio2: rk817_gt_gpio2 {
- pins = "gpio_gt";
- function = "pin_fun1";
- };
-
- rk817_pin_ts: rk817_pin_ts {
- pins = "gpio_ts";
- function = "pin_fun0";
- };
-
- rk817_pin_gt: rk817_pin_gt {
- pins = "gpio_gt";
- function = "pin_fun0";
- };
-
- rk817_slppin_null: rk817_slppin_null {
- pins = "gpio_slp";
- function = "pin_fun0";
- };
-
- rk817_slppin_slp: rk817_slppin_slp {
- pins = "gpio_slp";
- function = "pin_fun1";
- };
-
- rk817_slppin_pwrdn: rk817_slppin_pwrdn {
- pins = "gpio_slp";
- function = "pin_fun2";
- };
-
- rk817_slppin_rst: rk817_slppin_rst {
- pins = "gpio_slp";
- function = "pin_fun3";
- };
- };
+ vcc8-supply = <&vccsys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-suspend-microvolt = <3000000>;
};
};
- };
- battery {
- compatible = "rk817,battery";
- ocv_table = <3500 3625 3685 3697 3718 3735 3748
- 3760 3774 3788 3802 3816 3834 3853
- 3877 3908 3946 3975 4018 4071 4106>;
-
- /* KPL605475 Battery Spec */
- /*
- Capacity : 3.7V 3000mA
- Normal Voltage = 3.7V
- Cut-Off Voltage : 3.1V
- Internal Impedance : 180 mOhm
- Charging Voltage : 4.2V
- Charging Voltage Max : 4.25V
- Sample resister : 10 mohm
- */
- design_capacity = <3000>;
- design_qmax = <3000>;
- bat_res = <180>;
- sleep_enter_current = <300>;
- sleep_exit_current = <300>;
- sleep_filter_current = <100>;
- power_off_thresd = <3500>;
- zero_algorithm_vol = <3700>;
- max_soc_offset = <60>;
- monitor_sec = <5>;
- virtual_power = <0>;
- sample_res = <10>;
- };
-
- charger {
- compatible = "rk817,charger";
- min_input_voltage = <4500>;
- max_input_current = <1500>;
- max_chrg_current = <2000>;
- max_chrg_voltage = <4200>;
- chrg_term_mode = <0>;
- chrg_finish_cur = <300>;
- virtual_power = <0>;
- sample_res = <10>;
-
- /* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
- dc_det_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
- chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-
- extcon = <&u2phy>;
+ usb_midu: BOOST {
+ regulator-name = "usb_midu";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
rk817_codec: codec {
- #sound-dai-cells = <0>;
- compatible = "rockchip,rk817-codec";
- clocks = <&cru SCLK_I2S1_OUT>;
- clock-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&i2s1_2ch_mclk>;
- hp-volume = <20>;
- spk-volume = <3>;
- status = "okay";
+ rockchip,mic-in-differential;
};
};
};
};
&sdmmc {
- bus-width = <4>;
cap-sd-highspeed;
card-detect-delay = <200>;
cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
u-boot,dm-pre-reloc;
};
+&emmc_phy {
+ u-boot,dm-pre-reloc;
+};
+
&grf {
u-boot,dm-pre-reloc;
};
mmc1 = &sdmmc0;
};
+ chosen {
+ u-boot,spl-boot-order = &sdhci, &sdmmc0;
+ };
+
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
u-boot,dm-pre-reloc;
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&sdmmc0 {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ u-boot,dm-spl;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
+ */
+
+/ {
+ aliases {
+ spi0 = &rpc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cpg {
+ u-boot,dm-pre-reloc;
+};
+
+&ehci0 {
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+};
+
+&ehci1 {
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+};
+
+&extal_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&prr {
+ u-boot,dm-pre-reloc;
+};
+
+&rpc {
+ compatible = "renesas,rcar-gen3-rpc";
+ num-cs = <1>;
+ spi-max-frequency = <40000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&sdhi0 {
+ /delete-property/ cd-gpios;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ max-frequency = <208000000>;
+};
+
+&sdhi2 {
+ status = "disabled";
+};
+
+&sdhi3 {
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+};
};
};
+
+ðernet0 {
+ mdio0 {
+ ethernet-phy@7 {
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <1000>;
+ };
+ };
+};
+
&sdmmc1 {
u-boot,dm-spl;
};
/ {
aliases {
mmc0 = &mmc0;
-#if CONFIG_MMC_SUNXI_EXTRA_SLOT == 2
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
mmc1 = &mmc2;
#endif
};
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64
+ select SUPPORT_SPL
+ select SPL
select CLK
select PINCTRL
select RAM
switch (boot_mode) {
case BOOT_FASTBOOT:
debug("%s: enter fastboot!\n", __func__);
- env_set("preboot", "setenv preboot; fastboot usb0");
+ env_set("preboot", "setenv preboot; fastboot usb 0");
break;
case BOOT_UMS:
debug("%s: enter UMS!\n", __func__);
* PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
PX30.Core C.TOUCH Carrier board.
+ PX30.Core CTOUCH2-OF10:
+ * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+ * CTOUCH2.0 is a general purpose Carrier board with capacitive
+ touch interface support.
+ * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
+ * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
+ 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
-#define PMUGRF_BASE 0xfdc20000
-#define GRF_BASE 0xfdc60000
-
+#define PMUGRF_BASE 0xfdc20000
+#define GRF_BASE 0xfdc60000
+#define GRF_GPIO1B_DS_2 0x218
+#define GRF_GPIO1B_DS_3 0x21c
+#define GRF_GPIO1C_DS_0 0x220
+#define GRF_GPIO1C_DS_1 0x224
+#define GRF_GPIO1C_DS_2 0x228
+#define GRF_GPIO1C_DS_3 0x22c
+#define SGRF_BASE 0xFDD18000
+#define SGRF_SOC_CON4 0x10
+#define EMMC_HPROT_SECURE_CTRL 0x03
+#define SDMMC0_HPROT_SECURE_CTRL 0x01
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
int arch_cpu_init(void)
{
+#ifdef CONFIG_SPL_BUILD
+ /* Set the emmc sdmmc0 to secure */
+ rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
+ | SDMMC0_HPROT_SECURE_CTRL << 4));
+ /* set the emmc driver strength to level 2 */
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+#endif
return 0;
}
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
#ifndef _SOCFPGA_MISC_H_
#endif
void do_bridge_reset(int enable, unsigned int mask);
+void force_periph_program(unsigned int status);
+bool is_regular_boot_valid(void);
+bool is_periph_program_force(void);
+void set_regular_boot(unsigned int status);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
+int qspi_flash_software_reset(void);
#endif /* _SOCFPGA_MISC_H_ */
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
#ifndef _RESET_MANAGER_ARRIA10_H_
#define RSTMGR_A10_PER1MODRST 0x28
#define RSTMGR_A10_BRGMODRST 0x2c
#define RSTMGR_A10_SYSMODRST 0x30
+#define RSTMGR_A10_SYSWARMMASK 0x50
#define RSTMGR_CTRL RSTMGR_A10_CTRL
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
+#define ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK BIT(3)
+#define ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK BIT(4)
+
#endif /* _RESET_MANAGER_ARRIA10_H_ */
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
*/
#ifndef _SYSTEM_MANAGER_ARRIA10_H_
#define SYSMGR_A10_NOC_IDLEACK 0xd0
#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
+#define SYSMGR_A10_ROMCODE_CTRL 0x204
+#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
+#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND 0x208
+#define SYSMGR_A10_ISW_HANDOFF_BASE 0x230
+#define SYSMGR_A10_ISW_HANDOFF_7 0x1c
#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
#include <altera.h>
#include <miiphy.h>
#include <netdev.h>
#include <ns16550.h>
+#include <spi_flash.h>
#include <watchdog.h>
#include <asm/arch/misc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/nic301.h>
#include <asm/io.h>
#include <asm/pl310.h>
+#include <linux/sizes.h>
#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
+#define REGULAR_BOOT_MAGIC 0xd15ea5e
+#define PERIPH_RBF_PROG_FORCE 0x50455249
+
+#define QSPI_S25FL_SOFT_RESET_COMMAND 0x00f0ff82
+#define QSPI_N25_SOFT_RESET_COMMAND 0x00000001
+#define QSPI_NO_SOFT_RESET 0x00000000
+
/*
* FPGA programming support for SoC FPGA Arria 10
*/
else
socfpga_bridges_reset();
}
+
+/*
+ * This function set/unset flag with number "0x50455249" to
+ * handoff register isw_handoff[7] - 0xffd0624c
+ * This flag is used to force periph RBF program regardless FPGA status
+ * and double periph RBF config are needed on some devices or boards to
+ * stabilize the IO config system.
+ */
+void force_periph_program(unsigned int status)
+{
+ if (status)
+ writel(PERIPH_RBF_PROG_FORCE, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+ else
+ writel(0, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+}
+
+/*
+ * This function is used to check whether
+ * handoff register isw_handoff[7] contains
+ * flag for forcing the periph RBF program "0x50455249".
+ */
+bool is_periph_program_force(void)
+{
+ unsigned int status;
+
+ status = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+
+ if (status == PERIPH_RBF_PROG_FORCE)
+ return true;
+ else
+ return false;
+}
+
+/*
+ * This function set/unset magic number "0xd15ea5e" to
+ * handoff register isw_handoff[7] - 0xffd0624c
+ * This magic number is part of boot progress tracking
+ * and it's required for warm reset workaround on MPFE hang issue.
+ */
+void set_regular_boot(unsigned int status)
+{
+ if (status)
+ writel(REGULAR_BOOT_MAGIC, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+ else
+ writel(0, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+}
+
+/*
+ * This function is used to check whether
+ * handoff register isw_handoff[7] contains
+ * magic number "0xd15ea5e".
+ */
+bool is_regular_boot_valid(void)
+{
+ unsigned int status;
+
+ status = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+
+ if (status == REGULAR_BOOT_MAGIC)
+ return true;
+ else
+ return false;
+}
+
+#if IS_ENABLED(CONFIG_CADENCE_QSPI)
+/* This function is used to trigger software reset
+ * to the QSPI flash. On some boards, the QSPI flash reset may
+ * not be connected to the HPS warm reset.
+ */
+int qspi_flash_software_reset(void)
+{
+ struct udevice *flash;
+ int ret;
+
+ /* Get the flash info */
+ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED,
+ CONFIG_SF_DEFAULT_MODE,
+ &flash);
+
+ if (ret) {
+ debug("Failed to initialize SPI flash at ");
+ debug("%u:%u (error %d)\n", CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS, ret);
+ return -ENODEV;
+ }
+
+ if (!flash)
+ return -EINVAL;
+
+ /*
+ * QSPI flash software reset command, for the case where
+ * no HPS reset connected to QSPI flash reset
+ */
+ if (!memcmp(flash->name, "N25", SZ_1 + SZ_2))
+ writel(QSPI_N25_SOFT_RESET_COMMAND, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND);
+ else if (!memcmp(flash->name, "S25FL", SZ_1 + SZ_4))
+ writel(QSPI_S25FL_SOFT_RESET_COMMAND,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND);
+ else /* No software reset */
+ writel(QSPI_NO_SOFT_RESET, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND);
+
+ return 0;
+}
+#endif
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2021 Altera Corporation <www.altera.com>
*/
#include <common.h>
#include <asm/arch/fpga_manager.h>
#include <mmc.h>
#include <memalign.h>
+#include <linux/delay.h>
#define FPGA_BUFSIZ 16 * 1024
+#define FSBL_IMAGE_IS_VALID 0x49535756
+
+#define FSBL_IMAGE_IS_INVALID 0x0
+#define BOOTROM_CONFIGURES_IO_PINMUX 0x3
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
+ int ret;
+
ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
/* enable console uart printing */
/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
if (is_fpgamgr_user_mode()) {
- int ret = config_pins(gd->fdt_blob, "shared");
-
+ ret = config_pins(gd->fdt_blob, "shared");
if (ret)
return;
} else if (!is_fpgamgr_early_user_mode()) {
/* Program IOSSM(early IO release) or full FPGA */
fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+
+ /* Skipping double program for combined RBF */
+ if (!is_fpgamgr_user_mode()) {
+ /*
+ * Expect FPGA entered early user mode, so
+ * the flag is set to re-program IOSSM
+ */
+ force_periph_program(true);
+
+ /* Re-program IOSSM to stabilize IO system */
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+
+ force_periph_program(false);
+ }
}
/* If the IOSSM/full FPGA is already loaded, start DDR */
- if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+ if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) {
+ if (!is_regular_boot_valid()) {
+ /*
+ * Ensure all signals in stable state before triggering
+ * warm reset. This value is recommended from stress
+ * test.
+ */
+ mdelay(10);
+
+#if IS_ENABLED(CONFIG_CADENCE_QSPI)
+ /*
+ * Trigger software reset to QSPI flash.
+ * On some boards, the QSPI flash reset may not be
+ * connected to the HPS warm reset.
+ */
+ qspi_flash_software_reset();
+#endif
+
+ ret = readl(socfpga_get_rstmgr_addr() +
+ RSTMGR_A10_SYSWARMMASK);
+ /*
+ * Masking s2f & FPGA manager module reset from warm
+ * reset
+ */
+ writel(ret & (~(ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
+ ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK)),
+ socfpga_get_rstmgr_addr() +
+ RSTMGR_A10_SYSWARMMASK);
+
+ /*
+ * BootROM will configure both IO and pin mux after a
+ * warm reset
+ */
+ ret = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_CTRL);
+ writel(ret | BOOTROM_CONFIGURES_IO_PINMUX,
+ socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_CTRL);
+
+ /*
+ * Up to here, image is considered valid and should be
+ * set as valid before warm reset is triggered
+ */
+ writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_INITSWSTATE);
+
+ /*
+ * Set this flag to scratch register, so that a proper
+ * boot progress before / after warm reset can be
+ * tracked by FSBL
+ */
+ set_regular_boot(true);
+
+ WATCHDOG_RESET();
+
+ reset_cpu();
+ }
+
+ /*
+ * Reset this flag to scratch register, so that a proper
+ * boot progress before / after warm reset can be
+ * tracked by FSBL
+ */
+ set_regular_boot(false);
+
+ ret = readl(socfpga_get_rstmgr_addr() +
+ RSTMGR_A10_SYSWARMMASK);
+
+ /*
+ * Unmasking s2f & FPGA manager module reset from warm
+ * reset
+ */
+ writel(ret | ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK |
+ ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK,
+ socfpga_get_rstmgr_addr() + RSTMGR_A10_SYSWARMMASK);
+
+ /*
+ * Up to here, MPFE hang workaround is considered done and
+ * should be reset as invalid until FSBL successfully loading
+ * SSBL, and prepare jumping to SSBL, then only setting as
+ * valid
+ */
+ writel(FSBL_IMAGE_IS_INVALID, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_INITSWSTATE);
+
ddr_calibration_sequence();
+ }
if (!is_fpgamgr_user_mode())
fpgamgr_program(buf, FPGA_BUFSIZ, 0);
config_dedicated_pins(gd->fdt_blob);
WATCHDOG_RESET();
}
+
+/* board specific function prior loading SSBL / U-Boot proper */
+void spl_board_prepare_for_boot(void)
+{
+ writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ROMCODE_INITSWSTATE);
+}
imply DM_I2C
imply SYS_I2C_OCORES
imply SPL_I2C
+
+if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+ default 0x505000
+
+config ENV_SIZE
+ default 0x20000
+
+config ENV_SECT_SIZE
+ default 0x10000
+
+endif # ENV_IS_IN_SPI_FLASH
u-boot,dm-spl;
};
+ config {
+ u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */
+ };
+
hfclk {
u-boot,dm-spl;
};
clocks = <&rtcclk>;
};
+&qspi0 {
+ u-boot,dm-spl;
+ flash@0 {
+ u-boot,dm-spl;
+ };
+};
+
&spi0 {
mmc@0 {
u-boot,dm-spl;
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
/dts-v1/;
-#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+#include "microchip-mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
- #address-cells = <2>;
- #size-cells = <2>;
- model = "Microchip MPFS Icicle Kit";
- compatible = "microchip,mpfs-icicle-kit";
+ model = "Microchip PolarFire-SoC Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- serial0 = &uart0;
- ethernet0 = &emac1;
+ serial1 = &uart1;
+ ethernet0 = &mac1;
};
chosen {
- stdout-path = "serial0";
+ stdout-path = "serial1";
};
- cpucomplex: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+ cpus {
timebase-frequency = <RTCCLK_FREQ>;
- cpu0: cpu@0 {
- clocks = <&clkcfg CLK_CPU>;
- compatible = "sifive,e51", "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
- status = "disabled";
- operating-points = <
- /* kHz uV */
- 600000 1100000
- 300000 950000
- 150000 750000
- >;
- cpu0intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu1: cpu@1 {
- clocks = <&clkcfg CLK_CPU>;
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- status = "okay";
- operating-points = <
- /* kHz uV */
- 600000 1100000
- 300000 950000
- 150000 750000
- >;
- cpu1intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu2: cpu@2 {
- clocks = <&clkcfg CLK_CPU>;
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <2>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- status = "okay";
- operating-points = <
- /* kHz uV */
- 600000 1100000
- 300000 950000
- 150000 750000
- >;
- cpu2intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
+ };
+
+ reserved-memory {
+ ranges;
+ #size-cells = <2>;
+ #address-cells = <2>;
+
+ fabricbuf0: fabricbuf@0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xae000000 0x0 0x2000000>;
+ label = "fabricbuf0-ddr-c";
};
- cpu3: cpu@3 {
- clocks = <&clkcfg CLK_CPU>;
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <3>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- status = "okay";
- operating-points = <
- /* kHz uV */
- 600000 1100000
- 300000 950000
- 150000 750000
- >;
- cpu3intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
+
+ fabricbuf1: fabricbuf@1 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xc0000000 0x0 0x8000000>;
+ label = "fabricbuf1-ddr-nc";
};
- cpu4: cpu@4 {
- clocks = <&clkcfg CLK_CPU>;
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <4>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- status = "okay";
- operating-points = <
- /* kHz uV */
- 600000 1100000
- 300000 950000
- 150000 750000
- >;
- cpu4intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
+
+ fabricbuf2: fabricbuf@2 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xd8000000 0x0 0x8000000>;
+ label = "fabricbuf2-ddr-nc-wcb";
};
};
- refclk: refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- clock-output-names = "msspllclk";
+
+ udmabuf0 {
+ compatible = "ikwzm,u-dma-buf";
+ device-name = "udmabuf-ddr-c0";
+ minor-number = <0>;
+ size = <0x0 0x2000000>;
+ memory-region = <&fabricbuf0>;
+ sync-mode = <3>;
+ };
+
+ udmabuf1 {
+ compatible = "ikwzm,u-dma-buf";
+ device-name = "udmabuf-ddr-nc0";
+ minor-number = <1>;
+ size = <0x0 0x8000000>;
+ memory-region = <&fabricbuf1>;
+ sync-mode = <3>;
+ };
+
+ udmabuf2 {
+ compatible = "ikwzm,u-dma-buf";
+ device-name = "udmabuf-ddr-nc-wcb0";
+ minor-number = <2>;
+ size = <0x0 0x8000000>;
+ memory-region = <&fabricbuf2>;
+ sync-mode = <3>;
};
- ddr: memory@80000000 {
+
+ ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
};
- soc: soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "microchip,mpfs-icicle-kit", "simple-bus";
- ranges;
- clint0: clint@2000000 {
- compatible = "riscv,clint0";
- interrupts-extended = <&cpu0intc 3 &cpu0intc 7
- &cpu1intc 3 &cpu1intc 7
- &cpu2intc 3 &cpu2intc 7
- &cpu3intc 3 &cpu3intc 7
- &cpu4intc 3 &cpu4intc 7>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- reg-names = "control";
- clock-frequency = <RTCCLK_FREQ>;
- };
- cachecontroller: cache-controller@2010000 {
- compatible = "sifive,fu540-c000-ccache", "cache";
- cache-block-size = <64>;
- cache-level = <2>;
- cache-sets = <1024>;
- cache-size = <2097152>;
- cache-unified;
- interrupt-parent = <&plic>;
- interrupts = <1 2 3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
- };
- plic: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "sifive,plic-1.0.0";
- reg = <0x0 0xc000000 0x0 0x4000000>;
- riscv,max-priority = <7>;
- riscv,ndev = <186>;
- interrupt-controller;
- interrupts-extended = <
- &cpu0intc 11
- &cpu1intc 11 &cpu1intc 9
- &cpu2intc 11 &cpu2intc 9
- &cpu3intc 11 &cpu3intc 9
- &cpu4intc 11 &cpu4intc 9>;
- };
- uart0: serial@20000000 {
- compatible = "ns16550a";
- reg = <0x0 0x20000000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <90>;
- clocks = <&clkcfg CLK_MMUART0>;
- status = "okay";
- };
- clkcfg: clkcfg@20002000 {
- compatible = "microchip,mpfs-clkcfg";
- reg = <0x0 0x20002000 0x0 0x1000>;
- reg-names = "mss_sysreg";
- clocks = <&refclk>;
- #clock-cells = <1>;
- clock-output-names = "cpu", "axi", "ahb", "envm",
- "mac0", "mac1", "mmc", "timer",
- "mmuart0", "mmuart1", "mmuart2",
- "mmuart3", "mmuart4", "spi0", "spi1",
- "i2c0", "i2c1", "can0", "can1", "usb",
- "reserved", "rtc", "qspi", "gpio0",
- "gpio1", "gpio2", "ddrc", "fic0",
- "fic1", "fic2", "fic3", "athena",
- "cfm";
- };
- emmc: mmc@20008000 {
- compatible = "cdns,sd4hc";
- reg = <0x0 0x20008000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <88 89>;
- pinctrl-names = "default";
- clocks = <&clkcfg CLK_MMC>;
- bus-width = <4>;
- cap-mmc-highspeed;
- mmc-ddr-3_3v;
- max-frequency = <200000000>;
- non-removable;
- no-sd;
- no-sdio;
- voltage-ranges = <3300 3300>;
- status = "okay";
- };
- sdcard: sd@20008000 {
- compatible = "cdns,sd4hc";
- reg = <0x0 0x20008000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <88>;
- pinctrl-names = "default";
- clocks = <&clkcfg CLK_MMC>;
- bus-width = <4>;
- disable-wp;
- cap-sd-highspeed;
- card-detect-delay = <200>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- max-frequency = <200000000>;
- status = "disabled";
- };
- uart1: serial@20100000 {
- compatible = "ns16550a";
- reg = <0x0 0x20100000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <91>;
- clocks = <&clkcfg CLK_MMUART1>;
- status = "okay";
- };
- uart2: serial@20102000 {
- compatible = "ns16550a";
- reg = <0x0 0x20102000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <92>;
- clocks = <&clkcfg CLK_MMUART2>;
- status = "okay";
- };
- uart3: serial@20104000 {
- compatible = "ns16550a";
- reg = <0x0 0x20104000 0x0 0x400>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupt-parent = <&plic>;
- interrupts = <93>;
- clocks = <&clkcfg CLK_MMUART3>;
- status = "okay";
- };
- i2c0: i2c@2010a000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "microchip,mpfs-mss-i2c";
- reg = <0x0 0x2010a000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <58>;
- clocks = <&clkcfg CLK_I2C0>;
- status = "disabled";
- };
- i2c1: i2c@2010b000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "microchip,mpfs-mss-i2c";
- reg = <0x0 0x2010b000 0x0 0x1000>;
- interrupt-parent = <&plic>;
- interrupts = <61>;
- clocks = <&clkcfg CLK_I2C1>;
- status = "disabled";
- pac193x@10 {
- compatible = "microchip,pac1934";
- reg = <0x10>;
- samp-rate = <64>;
- status = "disabled";
- ch1: channel0 {
- uohms-shunt-res = <10000>;
- rail-name = "VDD";
- channel_enabled;
- };
- ch2: channel1 {
- uohms-shunt-res = <10000>;
- rail-name = "VDDA25";
- channel_enabled;
- };
- ch3: channel2 {
- uohms-shunt-res = <10000>;
- rail-name = "VDD25";
- channel_enabled;
- };
- ch4: channel3 {
- uohms-shunt-res = <10000>;
- rail-name = "VDDA";
- channel_enabled;
- };
- };
- };
- emac0: ethernet@20110000 {
- compatible = "microchip,mpfs-mss-gem";
- reg = <0x0 0x20110000 0x0 0x2000>;
- interrupt-parent = <&plic>;
- interrupts = <64 65 66 67>;
- local-mac-address = [56 34 00 FC 00 02];
- phy-mode = "sgmii";
- clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
- clock-names = "pclk", "hclk";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- phy-handle = <&phy0>;
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x01>;
- };
- };
- emac1: ethernet@20112000 {
- compatible = "microchip,mpfs-mss-gem";
- reg = <0x0 0x20112000 0x0 0x2000>;
- interrupt-parent = <&plic>;
- interrupts = <70 71 72 73>;
- local-mac-address = [00 00 00 00 00 00];
- phy-mode = "sgmii";
- clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
- status = "okay";
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x40000000>;
+ clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
+ };
+};
- #address-cells = <1>;
- #size-cells = <0>;
- phy-handle = <&phy1>;
- phy1: ethernet-phy@9 {
- reg = <9>;
- ti,fifo-depth = <0x01>;
- };
- };
- gpio: gpio@20122000 {
- compatible = "microchip,mpfs-mss-gpio";
- interrupt-parent = <&plic>;
- interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
- 27 28 29 30 31 32 33 34 35 36 37 38 39
- 40 41 42 43 44>;
- gpio-controller;
- clocks = <&clkcfg CLK_GPIO2>;
- reg = <0x00 0x20122000 0x0 0x1000>;
- reg-names = "control";
- #gpio-cells = <2>;
- status = "disabled";
+&uart1 {
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+
+ bus-width = <4>;
+ disable-wp;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ pac193x: pac193x@10 {
+ compatible = "microchip,pac1934";
+ reg = <0x10>;
+ samp-rate = <64>;
+ status = "okay";
+ ch1: channel0 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDDREG";
+ channel_enabled;
+ };
+ ch2: channel1 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDDA25";
+ channel_enabled;
+ };
+ ch3: channel2 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDD25";
+ channel_enabled;
+ };
+ ch4: channel3 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDDA_REG";
+ channel_enabled;
};
};
};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ ti,fifo-depth = <0x1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+#include "dt-bindings/clock/microchip-mpfs-clock.h"
+#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h"
+#include "dt-bindings/interrupt-controller/riscv-hart.h"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire SoC";
+ compatible = "microchip,mpfs";
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ clocks = <&clkcfg CLK_CPU>;
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 600000 1100000
+ 300000 950000
+ 150000 750000
+ >;
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu1: cpu@1 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 600000 1100000
+ 300000 950000
+ 150000 750000
+ >;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu2: cpu@2 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 600000 1100000
+ 300000 950000
+ 150000 750000
+ >;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu3: cpu@3 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 600000 1100000
+ 300000 950000
+ 150000 750000
+ >;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ cpu4: cpu@4 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <4>;
+ riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 600000 1100000
+ 300000 950000
+ 150000 750000
+ >;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "microchip,mpfs-soc", "simple-bus";
+ ranges;
+
+ clint: clint@2000000 {
+ compatible = "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0xC000>;
+ interrupts-extended =
+ <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
+ &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
+ &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
+ &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
+ &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
+ };
+
+ cachecontroller: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_L2_METADATA_CORR
+ PLIC_INT_L2_METADATA_UNCORR
+ PLIC_INT_L2_DATA_CORR>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
+ pdma: pdma@3000000 {
+ compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
+ PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
+ PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
+ PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
+ #dma-cells = <1>;
+ };
+
+ plic: interrupt-controller@c000000 {
+ compatible = "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ #interrupt-cells = <1>;
+ riscv,ndev = <186>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc HART_INT_M_EXT
+ &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
+ &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
+ &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
+ &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
+ };
+
+ refclk: refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ clock-output-names = "msspllclk";
+ };
+
+ clkcfg: clkcfg@20002000 {
+ compatible = "microchip,mpfs-clkcfg";
+ reg = <0x0 0x20002000 0x0 0x1000>;
+ reg-names = "mss_sysreg";
+ clocks = <&refclk>;
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
+ "mac0", "mac1", "mmc", "timer", /* 4-7 */
+ "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
+ "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
+ "i2c1", "can0", "can1", "usb", /* 16-19 */
+ "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
+ "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
+ "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
+ };
+
+ /* Common node entry for eMMC/SD */
+ mmc: mmc@20008000 {
+ compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
+ reg = <0x0 0x20008000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_MMC>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ uart0: serial@20000000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20000000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MMUART0>;
+ clocks = <&clkcfg CLK_MMUART0>;
+ status = "disabled"; /* Reserved for the HSS */
+ };
+
+ uart1: serial@20100000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20100000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MMUART1>;
+ clocks = <&clkcfg CLK_MMUART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@20102000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20102000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MMUART2>;
+ clocks = <&clkcfg CLK_MMUART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@20104000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20104000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MMUART3>;
+ clocks = <&clkcfg CLK_MMUART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@20106000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20106000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MMUART4>;
+ clocks = <&clkcfg CLK_MMUART4>;
+ status = "disabled";
+ };
+
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_SPI0>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_SPI0>;
+ num-cs = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_SPI1>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_SPI1>;
+ num-cs = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_I2C0>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_I2C0_MAIN>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_I2C1>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_I2C1_MAIN>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ can0: can@2010c000 {
+ compatible = "microchip,mpfs-can-uio";
+ reg = <0x0 0x2010c000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_CAN0>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_CAN0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ can1: can@2010d000 {
+ compatible = "microchip,mpfs-can-uio";
+ reg = <0x0 0x2010d000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_CAN1>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_CAN1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mac0: ethernet@20110000 {
+ compatible = "cdns,macb";
+ reg = <0x0 0x20110000 0x0 0x2000>;
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
+ clock-names = "pclk", "hclk";
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MAC0_INT
+ PLIC_INT_MAC0_QUEUE1
+ PLIC_INT_MAC0_QUEUE2
+ PLIC_INT_MAC0_QUEUE3
+ PLIC_INT_MAC0_EMAC
+ PLIC_INT_MAC0_MMSL>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mac1: ethernet@20112000 {
+ compatible = "cdns,macb";
+ reg = <0x0 0x20112000 0x0 0x2000>;
+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
+ clock-names = "pclk", "hclk";
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MAC1_INT
+ PLIC_INT_MAC1_QUEUE1
+ PLIC_INT_MAC1_QUEUE2
+ PLIC_INT_MAC1_QUEUE3
+ PLIC_INT_MAC1_EMAC
+ PLIC_INT_MAC1_MMSL>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ reg-names = "control";
+ clocks = <&clkcfg CLK_GPIO0>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ reg-names = "control";
+ clocks = <&clkcfg CLK_GPIO1>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ reg-names = "control";
+ clocks = <&clkcfg CLK_GPIO2>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-usb-host";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ reg-names = "mc","control";
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
+ interrupt-names = "dma","mc";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ qspi: qspi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_QSPI>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_QSPI>;
+ num-cs = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_G5C_MESSAGE>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_FABRIC_F2H_2>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ mchp,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mboxes = <&mbox 0>;
+ };
+
+ hwrandom: hwrandom {
+ compatible = "microchip,mpfs-rng";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscontroller = <&syscontroller>;
+ };
+
+ serialnum: serialnum {
+ compatible = "microchip,mpfs-serial-number";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscontroller = <&syscontroller>;
+ };
+
+ fpgadigest: fpgadigest {
+ compatible = "microchip,mpfs-digest";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscontroller = <&syscontroller>;
+ };
+
+ devicecert: cert {
+ compatible = "microchip,mpfs-device-cert";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscontroller = <&syscontroller>;
+ };
+
+ signature: signature {
+ compatible = "microchip,mpfs-signature";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscontroller = <&syscontroller>;
+ };
+ };
+};
compatible = "sandbox,clk-ccf";
};
+ efi-media {
+ compatible = "sandbox,efi-media";
+ };
+
eth@10002000 {
compatible = "sandbox,eth";
reg = <0x10002000 0x1000>;
F: board/beacon/beacon-rzg2m/
F: include/configs/beacon-rzg2m.h
F: configs/rzg2_beacon_defconfig
+F: arch/arm/dts/beacon-renesom-baseboard.dtsi
+F: arch/arm/dts/beacon-renesom-som.dtsi
+F: arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
+F: arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+F: arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+F: arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
+F: arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
+F: arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
+F: arch/arm/dts/rz-g2-beacon-u-boot.dtsi
+
ofnode node;
int i, ret;
+ brdcode = 0;
+ ddr3code = 0;
+ somcode = 0;
+
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
printf("%s: no /config node?\n", __func__);
return;
}
- brdcode = 0;
- ddr3code = 0;
- somcode = 0;
-
ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+ gpio_free_list_nodev(gpio, ret);
+
ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
+ gpio_free_list_nodev(gpio, ret);
+
ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
for (i = 0; i < ret; i++)
brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
+ gpio_free_list_nodev(gpio, ret);
+
printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
somcode, ddr3code, brdcode);
}
S: Maintained
F: configs/px30-core-ctouch2-px30_defconfig
+PX30-Core-CTOUCH2.0-OF10
+M: Jagan Teki <jagan@amarulasolutions.com>
+M: Suniel Mahesh <sunil@amarulasolutions.com>
+S: Maintained
+F: configs/px30-core-ctouch2-of10-px30_defconfig
+
PX30-Core-EDIMM2.2
M: Jagan Teki <jagan@amarulasolutions.com>
M: Suniel Mahesh <sunil@amarulasolutions.com>
imply MMC_WRITE
imply MMC_SDHCI
imply MMC_SDHCI_CADENCE
+ imply MMC_SDHCI_ADMA
+ imply MMC_HS200_SUPPORT
+ imply CMD_I2C
+ imply DM_I2C
+ imply SYS_I2C_MICROCHIP
endif
if (icicle_mac_addr[idx] == ':')
icicle_mac_addr[idx] = ' ';
}
- env_set("icicle_mac_addr", icicle_mac_addr);
+ env_set("icicle_mac_addr0", icicle_mac_addr);
+
+ mac_addr[5] = device_serial_number[0] + 1;
+
+ icicle_mac_addr[0] = '[';
+
+ sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
+
+ icicle_mac_addr[18] = ']';
+ icicle_mac_addr[19] = '\0';
+
+ for (idx = 0; idx < 20; idx++) {
+ if (icicle_mac_addr[idx] == ':')
+ icicle_mac_addr[idx] = ' ';
+ }
+ env_set("icicle_mac_addr1", icicle_mac_addr);
return 0;
}
#endif
/*
- * https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
+ * https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#raspberry-pi-revision-codes
*/
struct rpi_model {
const char *name;
DTB_DIR "bcm2711-rpi-4-b.dtb",
true,
},
+ [0x12] = {
+ "Zero 2 W",
+ DTB_DIR "bcm2837-rpi-zero-2.dtb",
+ false,
+ },
[0x13] = {
"400",
DTB_DIR "bcm2711-rpi-400.dtb",
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SIFIVE_FU740
+ select ENV_IS_IN_SPI_FLASH
select SUPPORT_SPL
select RESET_SIFIVE
select BINMAN
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
#define MODE_SELECT_REG 0x1000
+#define MODE_SELECT_SPI 0x6
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
u32 boot_device = mode_select & MODE_SELECT_MASK;
switch (boot_device) {
+ case MODE_SELECT_SPI:
+ return BOOT_DEVICE_SPI;
case MODE_SELECT_SD:
return BOOT_DEVICE_MMC1;
default:
return ret;
}
- ret = sun4i_usb_phy_vbus_detect(&phy);
- if (ret == 1) {
- pr_err("A charger is plugged into the OTG\n");
- return -ENODEV;
- }
-
- return ret;
+ return sun4i_usb_phy_vbus_detect(&phy);
}
#endif
Here is the step-by-step to boot to U-Boot on rk3399.
-Get the Source and build ATF/Cortex-M0 binaries
-===============================================
+Get the Source and build ATF binary
+===================================
- > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
- > git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
+ > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
Compile the ATF
===============
- > cd arm-trusted-firmware
+ > cd trusted-firmware-a
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
- > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin
-
-Compile the M0 firmware
-=======================
-
- > cd ../rk3399-cortex-m0
- > make CROSS_COMPILE=arm-cortex_m0-eabi-
- > cp rk3399m0.bin ../u-boot
+ > cp build/rk3399/release/bl31/bl31.elf ../u-boot/bl31.elf
Compile the U-Boot
==================
Package the image
=================
-Creating a SPL image for SD-Card/eMMC
- > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img
-Creating a SPL image for SPI-NOR
- > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
-Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
- > make CROSS_COMPILE=aarch64-linux-gnu-
+The SPL image for SD-Card/eMMC is readily available in idbloader.img at the
+root of U-Boot after compilation.
+
+Creating an SPL image for SPI-NOR:
+ > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader-spi.img
Flash the image
===============
Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
-image to offset 256k card.
+image to offset 256k.
SD-Card
-------
- > dd if=spl_mmc.img of=/dev/sdb seek=64
+ > dd if=idbloader.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
eMMC
> cd rkdeveloptool
> autoreconf -i && ./configure && make
> git clone https://github.com/rockchip-linux/rkbin.git
- > ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
- > ./rkdeveloptool wl 64 ../spl_mmc.img
+ > cd rkbin
+ > ./tools/boot_merger RKBOOT/RK3399MINIALL.ini
+ > cd ..
+ > ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin
+ > ./rkdeveloptool wl 64 ../idbloader.img
> ./rkdeveloptool wl 512 ../u-boot.itb
NOR-Flash
---------
-Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity
-we assume you have a SD-Card with a partition containing the required files
-ready.
-
- > load mmc 1:1 ${kernel_addr_r} spl_nor.img
- > sf probe
- > sf erase 0 +$filesize
- > sf write $kernel_addr_r 0 ${filesize}
- > load mmc 1:1 ${kernel_addr_r} u-boot.itb
- > sf erase 0x40000 +$filesize
- > sf write $kernel_addr_r 0x40000 ${filesize}
-
+rkdeveloptool allows to flash the on-board SPI via the USB OTG interface with
+help of the Rockchip loader binary.
-Reboot the system and you should see a U-Boot console on UART0 (115200n8).
+ > git clone https://github.com/rockchip-linux/rkdeveloptool
+ > cd rkdeveloptool
+ > autoreconf -i && ./configure && make
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > cd rkbin
+ > ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini
+ > cd ..
+ > ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin
+ > ./rkdeveloptool ef
+ > ./rkdeveloptool wl 0 ../idbloader-spi.img
+ > ./rkdeveloptool wl 512 ../u-boot.itb
DECLARE_GLOBAL_DATA_PTR;
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
/**
* image_get_ramdisk - get and verify ramdisk image
* @rd_addr: ramdisk image start address
return rd_hdr;
}
+#endif
/*****************************************************************************/
/* Shared dual-format routines */
static int select_ramdisk(bootm_headers_t *images, const char *select, u8 arch,
ulong *rd_datap, ulong *rd_lenp)
{
- ulong rd_addr = 0;
+ ulong rd_addr;
char *buf;
- const char *fit_uname_config = images->fit_uname_cfg;
- const char *fit_uname_ramdisk = NULL;
- bool processed;
- int rd_noffset;
- if (select) {
- ulong default_addr;
- bool done = true;
+#if CONFIG_IS_ENABLED(FIT)
+ const char *fit_uname_config = images->fit_uname_cfg;
+ const char *fit_uname_ramdisk = NULL;
+ int rd_noffset;
- if (CONFIG_IS_ENABLED(FIT)) {
+ if (select) {
+ ulong default_addr;
/*
* If the init ramdisk comes from the FIT image and
* the FIT image address is omitted in the command
else
default_addr = image_load_addr;
- if (fit_parse_conf(select, default_addr, &rd_addr,
- &fit_uname_config)) {
+ if (fit_parse_conf(select, default_addr,
+ &rd_addr, &fit_uname_config)) {
debug("* ramdisk: config '%s' from image at 0x%08lx\n",
fit_uname_config, rd_addr);
} else if (fit_parse_subimage(select, default_addr,
&fit_uname_ramdisk)) {
debug("* ramdisk: subimage '%s' from image at 0x%08lx\n",
fit_uname_ramdisk, rd_addr);
- } else {
- done = false;
+ } else
+#endif
+ {
+ rd_addr = hextoul(select, NULL);
+ debug("* ramdisk: cmdline image address = 0x%08lx\n",
+ rd_addr);
}
+#if CONFIG_IS_ENABLED(FIT)
+ } else {
+ /* use FIT configuration provided in first bootm
+ * command argument. If the property is not defined,
+ * quit silently (with -ENOPKG)
+ */
+ rd_addr = map_to_sysmem(images->fit_hdr_os);
+ rd_noffset = fit_get_node_from_config(images,
+ FIT_RAMDISK_PROP,
+ rd_addr);
+ if (rd_noffset == -ENOENT)
+ return -ENOPKG;
+ else if (rd_noffset < 0)
+ return rd_noffset;
}
- if (!done) {
- rd_addr = hextoul(select, NULL);
- debug("* ramdisk: cmdline image address = 0x%08lx\n",
- rd_addr);
- }
- } else if (CONFIG_IS_ENABLED(FIT)) {
- /* use FIT configuration provided in first bootm
- * command argument. If the property is not defined,
- * quit silently (with -ENOPKG )
- */
- rd_addr = map_to_sysmem(images->fit_hdr_os);
- rd_noffset = fit_get_node_from_config(images, FIT_RAMDISK_PROP,
- rd_addr);
- if (rd_noffset == -ENOENT)
- return -ENOPKG;
- else if (rd_noffset < 0)
- return rd_noffset;
- }
+#endif
- /*
- * Check if there is an initrd image at the
- * address provided in the second bootm argument
- * check image type, for FIT images get FIT node.
- */
- buf = map_sysmem(rd_addr, 0);
- processed = false;
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_LEGACY:
- if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
+ /*
+ * Check if there is an initrd image at the
+ * address provided in the second bootm argument
+ * check image type, for FIT images get FIT node.
+ */
+ buf = map_sysmem(rd_addr, 0);
+ switch (genimg_get_format(buf)) {
+#if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
+ case IMAGE_FORMAT_LEGACY: {
const image_header_t *rd_hdr;
printf("## Loading init Ramdisk from Legacy Image at %08lx ...\n",
rd_addr);
bootstage_mark(BOOTSTAGE_ID_CHECK_RAMDISK);
- rd_hdr = image_get_ramdisk(rd_addr, arch, images->verify);
+ rd_hdr = image_get_ramdisk(rd_addr, arch,
+ images->verify);
+
if (!rd_hdr)
return -ENOENT;
*rd_datap = image_get_data(rd_hdr);
*rd_lenp = image_get_data_size(rd_hdr);
- processed = true;
+ break;
}
- break;
- case IMAGE_FORMAT_FIT:
- if (CONFIG_IS_ENABLED(FIT)) {
- rd_noffset = fit_image_load(images, rd_addr,
- &fit_uname_ramdisk,
+#endif
+#if CONFIG_IS_ENABLED(FIT)
+ case IMAGE_FORMAT_FIT:
+ rd_noffset = fit_image_load(images,
+ rd_addr, &fit_uname_ramdisk,
&fit_uname_config, arch,
IH_TYPE_RAMDISK,
BOOTSTAGE_ID_FIT_RD_START,
images->fit_hdr_rd = map_sysmem(rd_addr, 0);
images->fit_uname_rd = fit_uname_ramdisk;
images->fit_noffset_rd = rd_noffset;
- processed = true;
- }
- break;
- case IMAGE_FORMAT_ANDROID:
- if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE)) {
+ break;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID:
android_image_get_ramdisk((void *)images->os.start,
rd_datap, rd_lenp);
- processed = true;
- }
- break;
- }
-
- if (!processed) {
- if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) {
- char *end = NULL;
-
- if (select)
- end = strchr(select, ':');
- if (end) {
- *rd_lenp = hextoul(++end, NULL);
- *rd_datap = rd_addr;
- processed = true;
+ break;
+#endif
+ default:
+ if (IS_ENABLED(CONFIG_SUPPORT_RAW_INITRD)) {
+ char *end = NULL;
+
+ if (select)
+ end = strchr(select, ':');
+ if (end) {
+ *rd_lenp = hextoul(++end, NULL);
+ *rd_datap = rd_addr;
+ break;
+ }
}
- }
-
- if (!processed) {
puts("Wrong Ramdisk Image Format\n");
return -EINVAL;
}
- }
return 0;
}
help
Print bytes from the hardware random number generator.
+config CMD_KASLRSEED
+ bool "kaslrseed"
+ depends on DM_RNG
+ help
+ Set the kaslr-seed in the chosen node with entropy provided by a
+ hardware random number generator.
+
config CMD_SLEEP
bool "sleep"
default y
obj-$(CONFIG_CMD_REISER) += reiser.o
obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
obj-$(CONFIG_CMD_RNG) += rng.o
+obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o
obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
obj-$(CONFIG_CMD_RTC) += rtc.o
obj-$(CONFIG_SANDBOX) += host.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'kaslrseed' command takes bytes from the hardware random number
+ * generator and uses them to set the kaslr-seed value in the chosen node.
+ *
+ * Copyright (c) 2021, Chris Morgan <macromorgan@hotmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <hexdump.h>
+#include <malloc.h>
+#include <rng.h>
+#include <fdt_support.h>
+
+static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ size_t n = 0x8;
+ struct udevice *dev;
+ u64 *buf;
+ int nodeoffset;
+ int ret = CMD_RET_SUCCESS;
+
+ if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+ printf("No RNG device\n");
+ return CMD_RET_FAILURE;
+ }
+
+ buf = malloc(n);
+ if (!buf) {
+ printf("Out of memory\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (dm_rng_read(dev, buf, n)) {
+ printf("Reading RNG failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!working_fdt) {
+ printf("No FDT memory address configured. Please configure\n"
+ "the FDT address via \"fdt addr <address>\" command.\n"
+ "Aborting!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = fdt_check_header(working_fdt);
+ if (ret < 0) {
+ printf("fdt_chosen: %s\n", fdt_strerror(ret));
+ return CMD_RET_FAILURE;
+ }
+
+ nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
+ if (nodeoffset < 0) {
+ printf("Reading chosen node failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
+ if (ret < 0) {
+ printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret));
+ return CMD_RET_FAILURE;
+ }
+
+ free(buf);
+
+ return ret;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char kaslrseed_help_text[] =
+ "[n]\n"
+ " - append random bytes to chosen kaslr-seed node\n";
+#endif
+
+U_BOOT_CMD(
+ kaslrseed, 1, 0, do_kaslr_seed,
+ "feed bytes from the hardware random number generator to the kaslr-seed",
+ kaslrseed_help_text
+);
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3568=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_MICROCHIP_ICICLE=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
-CONFIG_SBI_V01=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_FIT=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
+CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_PX30_CORE=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb"
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SOUND=y
+CONFIG_SYSRESET=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LCD=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_PX30_CORE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_PX30_CORE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
# CONFIG_CONSOLE_MUX is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_EFUSE=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
CONFIG_SPL_MMC=y
CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_AHCI=y
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_ID_EEPROM=y
CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_PWM=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=1
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
+CONFIG_SPI_FLASH_ISSI=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x54
CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
CONFIG_PHY=y
case IF_TYPE_VIRTIO:
puts("VirtIO");
break;
+ case IF_TYPE_EFI_MEDIA:
+ puts("EFI");
+ break;
default:
- puts ("UNKNOWN");
+ puts("UNKNOWN");
break;
}
printf (" device %d -- Partition Type: %s\n\n",
* Always should be done, otherwise hw partition 0 will return stale
* data after displaying a non-zero hw partition.
*/
- part_init(*dev_desc);
+ if ((*dev_desc)->if_type == IF_TYPE_MMC)
+ part_init(*dev_desc);
#endif
cleanup:
- Compile ATF
- For Puma board.
+ => git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ => cd arm-trusted-firmware
- => git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
- => cd arm-trusted-firmware
- => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+ (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
+ => make realclean
+ => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
- (export bl31.bin)
- => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.bin
-
- For rest of rk3399 boards.
-
- => git clone https://github.com/ARM-software/arm-trusted-firmware.git
- => cd arm-trusted-firmware
-
- (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
- => make realclean
- => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
-
- (export bl31.elf)
- => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
+ (export bl31.elf)
+ => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
- Compile PMU M0 firmware
- This is optional for most of the rk3399 boards and required only for Puma board.
+ This is optional for most of the rk3399 boards.
=> git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
=> cd rk3399-cortex-m0
--- /dev/null
+Calxeda Highbank/Midway board support
+=====================================
+
+The Calxeda ECX-1000 ("Highbank") and ECX-2000 ("Midway") were ARM based
+servers, providing high-density cluster systems. A single motherboard could
+host between 12 and 48 nodes, each with their own quad-core ARMv7
+processor, private DRAM and peripherals, connected through a high-bandwith
+and low-latency "fabric" network. Multiple motherboards could be connected
+together, to extend this fabric.
+
+For the purpose of U-Boot we just care about a single node, this can be
+used as a single system, just using the fabric to connect to some Ethernet
+network. Each node boots on its own, either from a local hard disk, or
+via the network.
+
+The earlier ECX-1000 nodes ("Highbank") contain four ARM Cortex-A9 cores,
+a Cortex-M3 system controller, three 10GBit/s MACs and five SATA
+controllers. The DRAM is limited to 4GB.
+
+The later ECX-2000 nodes ("Midway") use four Cortex-A15 cores, alongside
+two Cortex-A7 management cores, and support up to 32GB of DRAM, while
+keeping the other peripherals.
+
+For the purpose of U-Boot those two SoCs are very similar, so we offer
+one build target. The subtle differences are handled at runtime.
+Calxeda as a company is long defunct, and the remaining systems are
+considered legacy at this point.
+
+Bgilding U-Boot
+---------------
+There is only one defconfig to cover both systems::
+
+ $ make highbank_defconfig
+ $ make
+
+This will create ``u-boot.bin``, which could become part of the firmware update
+package, or could be chainloaded by the existing U-Boot, see below for more
+details.
+
+Boot process
+------------
+Upon powering up a node (which would be controlled by some BMC style
+management controller on the motherboard), the system controller ("ECME")
+would start and do some system initialisation (fabric registration,
+DRAM init, clock setup). It would load the device tree binary, some secure
+monitor code (``a9boot``/``a15boot``) and a U-Boot binary from SPI flash
+into DRAM, then power up the actual application cores (ARM Cortex-A9/A15).
+They would start executing ``a9boot``/``a15boot``, registering the PSCI SMC
+handlers, then dropping into U-Boot, but in non-secure state (HYP mode on
+the A15s).
+
+U-Boot would act as a mere loader, trying to find some ``boot.scr`` file on
+the local hard disks, or reverting to PXE boot.
+
+Updating U-Boot
+---------------
+The U-Boot binary is loaded from SPI flash, which is controlled exclusively
+by the ECME. This can be reached via IPMI using the LANplus transport protocol.
+Updating the SPI flash content requires vendor specific additions to the
+IPMI protocol, support for which was never upstreamed to ipmitool or
+FreeIPMI. Some older repositories for `ipmitool`_, the `pyipmi`_ library and
+a Python `management script`_ to update the SPI flash can be found on Github.
+
+A simpler and safer way to get an up-to-date U-Boot running, is chainloading
+it via the legacy U-Boot::
+
+ $ mkimage -A arm -O u-boot -T standalone -C none -a 0x8000 -e 0x8000 \
+ -n U-Boot -d u-boot.bin u-boot-highbank.img
+
+Then load this image file, either from hard disk, or via TFTP, from the
+existing U-Boot, and execute it with bootm::
+
+ => tftpboot 0x8000 u-boot-highbank.img
+ => bootm
+
+.. _`ipmitool`: https://github.com/Cynerva/ipmitool
+.. _`pyipmi`: https://pypi.org/project/pyipmi/
+.. _`management script`: https://github.com/Cynerva/cxmanage
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+Highbank
+========
+
+.. toctree::
+ :maxdepth: 2
+
+ highbank
coreboot/index
emulation/index
google/index
+ highbank/index
intel/index
kontron/index
microchip/index
2. Microchip Clock Driver.
3. Cadence MACB ethernet driver for networking support.
4. Cadence MMC Driver for eMMC/SD support.
+5. Microchip I2C Driver.
Booting from eMMC using HSS
---------------------------
Booting
~~~~~~~
-You should see the U-Boot prompt on UART0.
+You should see the U-Boot prompt on UART1.
+(Note: UART0 is reserved for HSS)
Sample boot log from MPFS Icicle Kit
''''''''''''''''''''''''''''''''''''
sudo dd if=<payload_binary> of=/dev/sdX2 bs=512
-You should see the U-Boot prompt on UART0.
+You should see the U-Boot prompt on UART1.
+(Note: UART0 is reserved for HSS)
GUID type
~~~~~~~~~
OpenEmbedded nodistro.0 unmatched ttySIF0
unmatched login:
+
+
+Booting from SPI
+----------------
+
+Use Building steps from "Booting from uSD using U-Boot SPL" section.
+
+Partition the SPI in Linux via mtdblock. The partition types here are
+"HiFive Unleashed FSBL", "HiFive Unleashed BBL", and "U-Boot environment"
+for partitions one through three respectively.
+
+.. code-block:: none
+
+ sgdisk --clear -a 1 \
+ --new=1:40:2087 --change-name=1:spl --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+ --new=2:2088:10279 --change-name=2:uboot --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+ --new=3:10280:10535 --change-name=3:env --typecode=3:3DE21764-95BD-54BD-A5C3-4ABE786F38A8 \
+ /dev/mtdblock0
+
+Write U-boot SPL and U-boot to their partitions.
+
+.. code-block:: none
+
+ dd if=u-boot-spl.bin of=/dev/mtdblock0 bs=4096 seek=5 conv=sync
+ dd if=u-boot.itb of=/dev/mtdblock0 bs=4096 seek=261 conv=sync
+
+Power off the board.
+
+Change DIP switches MSEL[3:0] to 0110.
+
+Power up the board.
A linker created list is used to keep track of the UEFI drivers. To create an
entry in the list the UEFI driver uses the U_BOOT_DRIVER macro specifying
-UCLASS_EFI as the ID of its uclass, e.g::
+UCLASS_EFI_LOADER as the ID of its uclass, e.g::
/* Identify as UEFI driver */
U_BOOT_DRIVER(efi_block) = {
.name = "EFI block driver",
- .id = UCLASS_EFI,
+ .id = UCLASS_EFI_LOADER,
.ops = &driver_ops,
};
The UEFI block IO driver supports devices exposing the EFI_BLOCK_IO_PROTOCOL.
When connected it creates a new U-Boot block IO device with interface type
-IF_TYPE_EFI, adds child controllers mapping the partitions, and installs the
-EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the
+IF_TYPE_EFI_LOADER, adds child controllers mapping the partitions, and installs
+the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the
software iPXE to boot from iSCSI network drives [4].
This driver is only available if U-Boot is configured with::
::
- => fdtaddr $fdtaddr
+ => fdt addr $fdtaddr
4. Grow it enough so it can encompass all applied overlays
help
This option enables the disk-block cache in TPL
+config EFI_MEDIA
+ bool "Support EFI media drivers"
+ default y if EFI || SANDBOX
+ help
+ Enable this to support media devices on top of UEFI. This enables
+ just the uclass so you also need a specific driver to make this do
+ anything.
+
+ For sandbox there is a test driver.
+
+if EFI_MEDIA
+
+config EFI_MEDIA_SANDBOX
+ bool "Sandbox EFI media driver"
+ depends on SANDBOX
+ default y
+ help
+ Enables a simple sandbox media driver, used for testing just the
+ EFI_MEDIA uclass. It does not do anything useful, since sandbox does
+ not actually support running on top of UEFI.
+
+config EFI_MEDIA_BLK
+ bool "EFI media block driver"
+ depends on EFI_APP
+ default y
+ help
+ Enables a block driver for providing access to UEFI devices. This
+ allows use of block devices detected by the underlying UEFI
+ implementation. With this it is possible to use filesystems on these
+ devices, for example.
+
+endif # EFI_MEDIA
+
config IDE
bool "Support IDE controllers"
select HAVE_BLOCK_DEVICE
endif
obj-$(CONFIG_SANDBOX) += sandbox.o
obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o
+
+obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o
+obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o
+obj-$(CONFIG_EFI_MEDIA_BLK) += efi_blk.o
[IF_TYPE_SATA] = "sata",
[IF_TYPE_HOST] = "host",
[IF_TYPE_NVME] = "nvme",
- [IF_TYPE_EFI] = "efi",
+ [IF_TYPE_EFI_MEDIA] = "efi",
+ [IF_TYPE_EFI_LOADER] = "efiloader",
[IF_TYPE_VIRTIO] = "virtio",
[IF_TYPE_PVBLOCK] = "pvblock",
};
[IF_TYPE_SATA] = UCLASS_AHCI,
[IF_TYPE_HOST] = UCLASS_ROOT,
[IF_TYPE_NVME] = UCLASS_NVME,
- [IF_TYPE_EFI] = UCLASS_EFI,
+ [IF_TYPE_EFI_MEDIA] = UCLASS_EFI_MEDIA,
+ [IF_TYPE_EFI_LOADER] = UCLASS_EFI_LOADER,
[IF_TYPE_VIRTIO] = UCLASS_VIRTIO,
[IF_TYPE_PVBLOCK] = UCLASS_PVBLOCK,
};
return 0;
}
+int blk_probe_or_unbind(struct udevice *dev)
+{
+ int ret;
+
+ ret = device_probe(dev);
+ if (ret) {
+ log_debug("probing %s failed\n", dev->name);
+ device_unbind(dev);
+ }
+
+ return ret;
+}
+
int blk_unbind_all(int if_type)
{
struct uclass *uc;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Uclass for EFI media devices
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+
+UCLASS_DRIVER(efi_media) = {
+ .id = UCLASS_EFI_MEDIA,
+ .name = "efi_media",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Block driver for EFI devices
+ * This supports a media driver of UCLASS_EFI with a child UCLASS_BLK
+ * It allows block-level access to EFI devices made available via EFI boot
+ * services
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <dm.h>
+#include <efi.h>
+#include <efi_api.h>
+
+struct efi_block_plat {
+ struct efi_block_io *blkio;
+};
+
+/**
+ * Read from block device
+ *
+ * @dev: device
+ * @blknr: first block to be read
+ * @blkcnt: number of blocks to read
+ * @buffer: output buffer
+ * Return: number of blocks transferred
+ */
+static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ struct efi_block_plat *plat = dev_get_plat(dev);
+ struct efi_block_io *io = plat->blkio;
+ efi_status_t ret;
+
+ log_debug("read buf=%p, block=%lx, count=%lx: ", buffer, (ulong)blknr,
+ (ulong)blkcnt);
+ ret = io->read_blocks(io, io->media->media_id, blknr,
+ blkcnt * io->media->block_size, buffer);
+ log_debug("ret=%lx (dec %ld)\n", ret & ~EFI_ERROR_MASK,
+ ret & ~EFI_ERROR_MASK);
+ if (ret)
+ return 0;
+
+ return blkcnt;
+}
+
+/**
+ * Write to block device
+ *
+ * @dev: device
+ * @blknr: first block to be write
+ * @blkcnt: number of blocks to write
+ * @buffer: input buffer
+ * Return: number of blocks transferred
+ */
+static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+{
+ struct efi_block_plat *plat = dev_get_plat(dev);
+ struct efi_block_io *io = plat->blkio;
+ efi_status_t ret;
+
+ log_debug("write buf=%p, block=%lx, count=%lx: ", buffer, (ulong)blknr,
+ (ulong)blkcnt);
+ ret = io->write_blocks(io, io->media->media_id, blknr,
+ blkcnt * io->media->block_size, (void *)buffer);
+ log_debug("ret=%lx (dec %ld)\n", ret & ~EFI_ERROR_MASK,
+ ret & ~EFI_ERROR_MASK);
+ if (ret)
+ return 0;
+
+ return blkcnt;
+}
+
+/* Block device driver operators */
+static const struct blk_ops efi_blk_ops = {
+ .read = efi_bl_read,
+ .write = efi_bl_write,
+};
+
+U_BOOT_DRIVER(efi_block) = {
+ .name = "efi_block",
+ .id = UCLASS_BLK,
+ .ops = &efi_blk_ops,
+ .plat_auto = sizeof(struct efi_block_plat),
+};
+
+static int efi_media_bind(struct udevice *dev)
+{
+ struct efi_media_plat *plat = dev_get_plat(dev);
+ struct efi_block_plat *blk_plat;
+ struct udevice *blk;
+ int ret;
+
+ ret = blk_create_devicef(dev, "efi_block", "blk", IF_TYPE_EFI_MEDIA,
+ dev_seq(dev), plat->blkio->media->block_size,
+ plat->blkio->media->last_block, &blk);
+ if (ret) {
+ debug("Cannot create block device\n");
+ return ret;
+ }
+ blk_plat = dev_get_plat(blk);
+ blk_plat->blkio = plat->blkio;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(efi_media) = {
+ .name = "efi_media",
+ .id = UCLASS_EFI_MEDIA,
+ .bind = efi_media_bind,
+ .plat_auto = sizeof(struct efi_media_plat),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * EFI_MEDIA driver for sandbox
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+
+static const struct udevice_id sandbox_efi_media_ids[] = {
+ { .compatible = "sandbox,efi-media" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_efi_media) = {
+ .name = "sandbox_efi_media",
+ .id = UCLASS_EFI_MEDIA,
+ .of_match = sandbox_efi_media_ids,
+};
* Copyright 2019 NXP
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
+#include <clk.h>
#include <clk-uclass.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
#include <dm/device.h>
#include <dm/devres.h>
#include <linux/clk-provider.h>
-#include <clk.h>
#include <linux/err.h>
#include "clk.h"
*
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <clk-uclass.h>
+#include <log.h>
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
#include <dm/lists.h>
+#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <linux/bug.h>
#include <linux/clk-provider.h>
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
if (width + shift > 16) {
- pr_warn("divider value exceeds LOWORD field\n");
+ dev_warn(dev, "divider value exceeds LOWORD field\n");
return ERR_PTR(-EINVAL);
}
}
*
* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
*/
+
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
-#include <malloc.h>
+#include <clk.h>
#include <clk-uclass.h>
+#include <div64.h>
+#include <log.h>
+#include <malloc.h>
#include <dm/device.h>
#include <dm/devres.h>
#include <linux/clk-provider.h>
-#include <div64.h>
-#include <clk.h>
-#include "clk.h"
#include <linux/err.h>
+#include "clk.h"
+
#define UBOOT_DM_CLK_IMX_FIXED_FACTOR "ccf_clk_fixed_factor"
static ulong clk_factor_recalc_rate(struct clk *clk)
* Gated clock implementation
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
-#include <asm/io.h>
-#include <malloc.h>
+#include <clk.h>
+#include <log.h>
#include <clk-uclass.h>
+#include <malloc.h>
+#include <asm/io.h>
#include <dm/device.h>
+#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/bitops.h>
#include <linux/clk-provider.h>
-#include <clk.h>
-#include "clk.h"
#include <linux/err.h>
+#include "clk.h"
+
#define UBOOT_DM_CLK_GATE "clk_gate"
/**
if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
if (bit_idx > 15) {
- pr_err("gate bit exceeds LOWORD field\n");
+ dev_err(dev, "gate bit exceeds LOWORD field\n");
return ERR_PTR(-EINVAL);
}
}
* clock.
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk.h>
#include <clk-uclass.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
#include <dm/device.h>
+#include <dm/device_compat.h>
#include <dm/devres.h>
#include <dm/uclass.h>
#include <linux/bitops.h>
-#include <malloc.h>
-#include <asm/io.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
+
#include "clk.h"
#define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux"
index = clk_fetch_parent_index(clk, parent);
if (index < 0) {
- printf("Could not fetch index\n");
+ log_err("Could not fetch index\n");
return index;
}
if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
width = fls(mask) - ffs(mask) + 1;
if (width + shift > 16) {
- pr_err("mux value exceeds LOWORD field\n");
+ dev_err(dev, "mux value exceeds LOWORD field\n");
return ERR_PTR(-EINVAL);
}
}
#include <errno.h>
#include <log.h>
#include <malloc.h>
+#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/devres.h>
#include <linux/bug.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
-#include <asm/global_data.h>
static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
{
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
+#include <clk.h>
#include <clk-uclass.h>
#include <log.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <dm/lists.h>
#include <dm/device-internal.h>
-#include <clk.h>
int clk_register(struct clk *clk, const char *drv_name,
const char *name, const char *parent_name)
ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
if (ret) {
- printf("%s: failed to get %s device (parent of %s)\n",
- __func__, parent_name, name);
+ log_err("%s: failed to get %s device (parent of %s)\n",
+ __func__, parent_name, name);
} else {
- debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
- parent->name, parent);
+ log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
+ parent->name, parent);
}
drv = lists_driver_lookup_name(drv_name);
if (!drv) {
- printf("%s: %s is not a valid driver name\n",
- __func__, drv_name);
+ log_err("%s: %s is not a valid driver name\n",
+ __func__, drv_name);
return -ENOENT;
}
ret = device_bind(parent, drv, name, NULL, ofnode_null(), &clk->dev);
if (ret) {
- printf("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
- ret);
+ log_err("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
+ ret);
return ret;
}
* Author: Anup Patel <anup.patel@wdc.com>
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk-uclass.h>
#include <div64.h>
#include <dm.h>
+#include <log.h>
#include <linux/err.h>
struct clk_fixed_factor {
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <log.h>
#include <dm/device-internal.h>
#include <linux/clk-provider.h>
if (strstr(uname, "fpga-periph") &&
(!is_fpgamgr_early_user_mode() ||
- is_fpgamgr_user_mode())) {
+ is_fpgamgr_user_mode() ||
+ is_periph_program_force())) {
fpga_node_name = uname;
printf("FPGA: Start to program ");
printf("peripheral/full bitstream ...\n");
internal buffer holding up to 8 bytes for transfers and supports
both 7-bit and 10-bit addresses.
+config SYS_I2C_MICROCHIP
+ bool "Microchip I2C driver"
+ help
+ Add support for the Microchip I2C driver. This is operating on
+ standard mode up to 100 kbits/s and fast mode up to 400 kbits/s.
+
config SYS_I2C_MXC
bool "NXP MXC I2C driver"
help
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
+obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o
obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Microchip I2C controller driver
+ *
+ * Copyright (C) 2021 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#define MICROCHIP_I2C_TIMEOUT (1000 * 60)
+
+#define MPFS_I2C_CTRL (0x00)
+#define CTRL_CR0 (0x00)
+#define CTRL_CR1 (0x01)
+#define CTRL_AA BIT(2)
+#define CTRL_SI BIT(3)
+#define CTRL_STO BIT(4)
+#define CTRL_STA BIT(5)
+#define CTRL_ENS1 BIT(6)
+#define CTRL_CR2 (0x07)
+#define MPFS_I2C_STATUS (0x04)
+#define STATUS_BUS_ERROR (0x00)
+#define STATUS_M_START_SENT (0x08)
+#define STATUS_M_REPEATED_START_SENT (0x10)
+#define STATUS_M_SLAW_ACK (0x18)
+#define STATUS_M_SLAW_NACK (0x20)
+#define STATUS_M_TX_DATA_ACK (0x28)
+#define STATUS_M_TX_DATA_NACK (0x30)
+#define STATUS_M_ARB_LOST (0x38)
+#define STATUS_M_SLAR_ACK (0x40)
+#define STATUS_M_SLAR_NACK (0x48)
+#define STATUS_M_RX_DATA_ACKED (0x50)
+#define STATUS_M_RX_DATA_NACKED (0x58)
+#define STATUS_S_SLAW_ACKED (0x60)
+#define STATUS_S_ARB_LOST_SLAW_ACKED (0x68)
+#define STATUS_S_GENERAL_CALL_ACKED (0x70)
+#define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED (0x78)
+#define STATUS_S_RX_DATA_ACKED (0x80)
+#define STATUS_S_RX_DATA_NACKED (0x88)
+#define STATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90)
+#define STATUS_S_GENERAL_CALL_RX_DATA_NACKED (0x98)
+#define STATUS_S_RX_STOP (0xA0)
+#define STATUS_S_SLAR_ACKED (0xA8)
+#define STATUS_S_ARB_LOST_SLAR_ACKED (0xB0)
+#define STATUS_S_TX_DATA_ACK (0xb8)
+#define STATUS_S_TX_DATA_NACK (0xC0)
+#define STATUS_LAST_DATA_ACK (0xC8)
+#define STATUS_M_SMB_MASTER_RESET (0xD0)
+#define STATUS_S_SCL_LOW_TIMEOUT (0xD8)
+#define STATUS_NO_STATE_INFO (0xF8)
+#define MPFS_I2C_DATA (0x08)
+#define MPFS_I2C_SLAVE0_ADDR (0x0c)
+#define MPFS_I2C_SMBUS (0x10)
+#define MPFS_I2C_FREQ (0x14)
+#define MPFS_I2C_GLITCHREG (0x18)
+#define MPFS_I2C_SLAVE1_ADDR (0x1c)
+
+#define PCLK_DIV_256 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
+#define PCLK_DIV_224 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
+#define PCLK_DIV_192 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
+#define PCLK_DIV_160 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
+#define PCLK_DIV_960 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
+#define PCLK_DIV_120 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
+#define PCLK_DIV_60 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
+#define BCLK_DIV_8 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
+#define CLK_MASK ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
+
+/*
+ * mpfs_i2c_bus - I2C bus context
+ * @base: pointer to register struct
+ * @msg_len: number of bytes transferred in msg
+ * @msg_err: error code for completed message
+ * @i2c_clk: clock reference for i2c input clock
+ * @clk_rate: current i2c bus clock rate
+ * @buf: ptr to msg buffer for easier use.
+ * @addr: i2c address.
+ * @isr_status: cached copy of local ISR status.
+ */
+struct mpfs_i2c_bus {
+ void __iomem *base;
+ size_t msg_len;
+ int msg_err;
+ struct clk i2c_clk;
+ u32 clk_rate;
+ u8 *buf;
+ u8 addr;
+ u32 isr_status;
+};
+
+static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
+{
+ return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
+}
+
+static void mpfs_i2c_int_clear(struct mpfs_i2c_bus *bus)
+{
+ u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ ctrl &= ~CTRL_SI;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+}
+
+static void mpfs_i2c_core_disable(struct mpfs_i2c_bus *bus)
+{
+ u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ ctrl &= ~CTRL_ENS1;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+}
+
+static void mpfs_i2c_core_enable(struct mpfs_i2c_bus *bus)
+{
+ u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ ctrl |= CTRL_ENS1;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+}
+
+static void mpfs_i2c_reset(struct mpfs_i2c_bus *bus)
+{
+ mpfs_i2c_core_disable(bus);
+ mpfs_i2c_core_enable(bus);
+}
+
+static inline void mpfs_i2c_stop(struct mpfs_i2c_bus *bus)
+{
+ u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ ctrl |= CTRL_STO;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+}
+
+static inline int mpfs_generate_divisor(u32 rate, u8 *code)
+{
+ int ret = 0;
+
+ if (rate >= 960)
+ *code = PCLK_DIV_960;
+ else if (rate >= 256)
+ *code = PCLK_DIV_256;
+ else if (rate >= 224)
+ *code = PCLK_DIV_224;
+ else if (rate >= 192)
+ *code = PCLK_DIV_192;
+ else if (rate >= 160)
+ *code = PCLK_DIV_160;
+ else if (rate >= 120)
+ *code = PCLK_DIV_120;
+ else if (rate >= 60)
+ *code = PCLK_DIV_60;
+ else if (rate >= 8)
+ *code = BCLK_DIV_8;
+ else
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static int mpfs_i2c_init(struct mpfs_i2c_bus *bus, struct udevice *dev)
+{
+ u32 clk_rate, divisor;
+ u8 clkval, ctrl;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &bus->i2c_clk);
+ if (ret)
+ return -EINVAL;
+
+ ret = clk_enable(&bus->i2c_clk);
+ if (ret)
+ return ret;
+
+ clk_rate = clk_get_rate(&bus->i2c_clk);
+ if (!clk_rate)
+ return -EINVAL;
+
+ clk_free(&bus->i2c_clk);
+
+ divisor = clk_rate / bus->clk_rate;
+
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ ctrl &= ~CLK_MASK;
+
+ ret = mpfs_generate_divisor(divisor, &clkval);
+ if (ret)
+ return -EINVAL;
+
+ ctrl |= clkval;
+
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ /* Reset I2C core */
+ mpfs_i2c_reset(bus);
+
+ return 0;
+}
+
+static void mpfs_i2c_transfer(struct mpfs_i2c_bus *bus, u32 data)
+{
+ if (bus->msg_len > 0)
+ writel(data, bus->base + MPFS_I2C_DATA);
+}
+
+static void mpfs_i2c_empty_rx(struct mpfs_i2c_bus *bus)
+{
+ u8 ctrl;
+ u8 data_read;
+
+ if (bus->msg_len > 0) {
+ data_read = readl(bus->base + MPFS_I2C_DATA);
+ *bus->buf++ = data_read;
+ bus->msg_len--;
+ }
+
+ if (bus->msg_len == 0) {
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ ctrl &= ~CTRL_AA;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+ }
+}
+
+static int mpfs_i2c_fill_tx(struct mpfs_i2c_bus *bus)
+{
+ mpfs_i2c_transfer(bus, *bus->buf++);
+ bus->msg_len--;
+
+ return 0;
+}
+
+static int mpfs_i2c_service_handler(struct mpfs_i2c_bus *bus)
+{
+ bool finish = false;
+ u32 status;
+ u8 ctrl;
+
+ status = bus->isr_status;
+
+ switch (status) {
+ case STATUS_M_START_SENT:
+ case STATUS_M_REPEATED_START_SENT:
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ ctrl &= ~CTRL_STA;
+ writel(bus->addr, bus->base + MPFS_I2C_DATA);
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+ break;
+ case STATUS_M_SLAW_ACK:
+ case STATUS_M_TX_DATA_ACK:
+ if (bus->msg_len > 0) {
+ mpfs_i2c_fill_tx(bus);
+ } else {
+ /* On the last byte to be transmitted, send STOP */
+ mpfs_i2c_stop(bus);
+ finish = true;
+ }
+ break;
+ case STATUS_M_SLAR_ACK:
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ ctrl |= CTRL_AA;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+ if (bus->msg_len == 0) {
+ /* On the last byte to be transmitted, send STOP */
+ mpfs_i2c_stop(bus);
+ finish = true;
+ }
+ break;
+ case STATUS_M_RX_DATA_ACKED:
+ mpfs_i2c_empty_rx(bus);
+ if (bus->msg_len == 0) {
+ /* On the last byte to be transmitted, send STOP */
+ mpfs_i2c_stop(bus);
+ finish = true;
+ }
+ break;
+ case STATUS_M_TX_DATA_NACK:
+ case STATUS_M_RX_DATA_NACKED:
+ case STATUS_M_SLAR_NACK:
+ case STATUS_M_SLAW_NACK:
+ bus->msg_err = -ENXIO;
+ mpfs_i2c_stop(bus);
+ finish = true;
+ break;
+
+ case STATUS_M_ARB_LOST:
+ /* Handle Lost Arbitration */
+ bus->msg_err = -EAGAIN;
+ finish = true;
+ break;
+ default:
+ break;
+ }
+
+ if (finish) {
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ ctrl &= ~CTRL_AA;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+ return 0;
+ }
+
+ return 1;
+}
+
+static int mpfs_i2c_service(struct mpfs_i2c_bus *bus)
+{
+ int ret = 0;
+ int si_bit;
+
+ si_bit = readl(bus->base + MPFS_I2C_CTRL);
+ if (si_bit & CTRL_SI) {
+ bus->isr_status = readl(bus->base + MPFS_I2C_STATUS);
+ ret = mpfs_i2c_service_handler(bus);
+ }
+ /* Clear the si flag */
+ mpfs_i2c_int_clear(bus);
+ si_bit = readl(bus->base + MPFS_I2C_CTRL);
+
+ return ret;
+}
+
+static int mpfs_i2c_check_service_change(struct mpfs_i2c_bus *bus)
+{
+ u8 ctrl;
+ u32 count = 0;
+
+ while (1) {
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ if (ctrl & CTRL_SI)
+ break;
+ udelay(1);
+ count += 1;
+ if (count == MICROCHIP_I2C_TIMEOUT)
+ return -ETIMEDOUT;
+ }
+ return 0;
+}
+
+static int mpfs_i2c_poll_device(struct mpfs_i2c_bus *bus)
+{
+ int ret;
+
+ while (1) {
+ ret = mpfs_i2c_check_service_change(bus);
+ if (ret)
+ return ret;
+
+ ret = mpfs_i2c_service(bus);
+ if (!ret)
+ /* all messages have been transferred */
+ return ret;
+ }
+}
+
+static int mpfs_i2c_xfer_msg(struct mpfs_i2c_bus *bus, struct i2c_msg *msg)
+{
+ u8 ctrl;
+ int ret;
+
+ if (!msg->len || !msg->buf)
+ return -EINVAL;
+
+ bus->addr = i2c_8bit_addr_from_msg(msg);
+ bus->msg_len = msg->len;
+ bus->buf = msg->buf;
+ bus->msg_err = 0;
+
+ mpfs_i2c_core_enable(bus);
+
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ ctrl |= CTRL_STA;
+
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+
+ ret = mpfs_i2c_poll_device(bus);
+ if (ret)
+ return ret;
+
+ return bus->msg_err;
+}
+
+static int mpfs_i2c_xfer(struct udevice *dev, struct i2c_msg *msgs, int num_msgs)
+{
+ struct mpfs_i2c_bus *bus = dev_get_priv(dev);
+ int idx, ret;
+
+ if (!msgs || !num_msgs)
+ return -EINVAL;
+
+ for (idx = 0; idx < num_msgs; idx++) {
+ ret = mpfs_i2c_xfer_msg(bus, msgs++);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int mpfs_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
+{
+ struct mpfs_i2c_bus *bus = dev_get_priv(dev);
+ int ret;
+ u8 ctrl, reg = 0;
+
+ /*
+ * Send the chip address and verify that the
+ * address was <ACK>ed.
+ */
+ bus->addr = addr << 1 | I2C_M_RD;
+ bus->buf = ®
+ bus->msg_len = 0;
+ bus->msg_err = 0;
+
+ mpfs_i2c_core_enable(bus);
+
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+
+ ctrl |= CTRL_STA;
+
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+
+ ret = mpfs_i2c_poll_device(bus);
+ if (ret)
+ return ret;
+
+ return bus->msg_err;
+}
+
+static int mpfs_i2c_probe(struct udevice *dev)
+{
+ int ret;
+ u32 val;
+ struct mpfs_i2c_bus *bus = dev_get_priv(dev);
+
+ bus->base = dev_read_addr_ptr(dev);
+ if (!bus->base)
+ return -EINVAL;
+
+ val = dev_read_u32(dev, "clock-frequency", &bus->clk_rate);
+ if (val) {
+ printf("Default to 100kHz\n");
+ /* default clock rate */
+ bus->clk_rate = 100000;
+ }
+
+ if (bus->clk_rate > 400000 || bus->clk_rate <= 0) {
+ printf("Invalid clock-frequency %d\n", bus->clk_rate);
+ return -EINVAL;
+ }
+
+ ret = mpfs_i2c_init(bus, dev);
+
+ return ret;
+}
+
+static const struct dm_i2c_ops mpfs_i2c_ops = {
+ .xfer = mpfs_i2c_xfer,
+ .probe_chip = mpfs_i2c_probe_chip,
+};
+
+static const struct udevice_id mpfs_i2c_ids[] = {
+ {.compatible = "microchip,mpfs-i2c"},
+ {}
+};
+
+U_BOOT_DRIVER(mpfs_i2c) = {
+ .name = "mpfs_i2c",
+ .id = UCLASS_I2C,
+ .of_match = mpfs_i2c_ids,
+ .ops = &mpfs_i2c_ops,
+ .probe = mpfs_i2c_probe,
+ .priv_auto = sizeof(struct mpfs_i2c_bus),
+};
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
struct i2c_msg *dmsg, *omsg, dummy;
+ u8 *addr_buf_ptr;
+ u8 addr_buf[4];
+ int i;
memset(&dummy, 0, sizeof(struct i2c_msg));
omsg = nmsgs == 1 ? &dummy : msg;
dmsg = nmsgs == 1 ? msg : msg + 1;
+ /* We need to swap the register address if its size is > 1 */
+ addr_buf_ptr = &addr_buf[0];
+ for (i = omsg->len; i > 0; i--)
+ *addr_buf_ptr++ = omsg->buf[i - 1];
+
if (dmsg->flags & I2C_M_RD)
- return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
+ return __twsi_i2c_read(dev->base, dmsg->addr, addr_buf,
omsg->len, dmsg->buf, dmsg->len,
dev->tick);
else
- return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
+ return __twsi_i2c_write(dev->base, dmsg->addr, addr_buf,
omsg->len, dmsg->buf, dmsg->len,
dev->tick);
}
eqos->tx_desc_idx = 0;
eqos->rx_desc_idx = 0;
- ret = eqos->config->ops->eqos_start_clks(dev);
- if (ret < 0) {
- pr_err("eqos_start_clks() failed: %d", ret);
- goto err;
- }
-
ret = eqos->config->ops->eqos_start_resets(dev);
if (ret < 0) {
pr_err("eqos_start_resets() failed: %d", ret);
- goto err_stop_clks;
+ goto err;
}
udelay(10);
phy_shutdown(eqos->phy);
err_stop_resets:
eqos->config->ops->eqos_stop_resets(dev);
-err_stop_clks:
- eqos->config->ops->eqos_stop_clks(dev);
err:
pr_err("FAILED: %d", ret);
return ret;
phy_shutdown(eqos->phy);
}
eqos->config->ops->eqos_stop_resets(dev);
- eqos->config->ops->eqos_stop_clks(dev);
debug("%s: OK\n", __func__);
}
goto err_remove_resources_core;
}
+ ret = eqos->config->ops->eqos_start_clks(dev);
+ if (ret < 0) {
+ pr_err("eqos_start_clks() failed: %d", ret);
+ goto err_remove_resources_tegra;
+ }
+
#ifdef CONFIG_DM_ETH_PHY
eqos->mii = eth_phy_get_mdio_bus(dev);
#endif
if (!eqos->mii) {
pr_err("mdio_alloc() failed");
ret = -ENOMEM;
- goto err_remove_resources_tegra;
+ goto err_stop_clks;
}
eqos->mii->read = eqos_mdio_read;
eqos->mii->write = eqos_mdio_write;
err_free_mdio:
mdio_free(eqos->mii);
+err_stop_clks:
+ eqos->config->ops->eqos_stop_clks(dev);
err_remove_resources_tegra:
eqos->config->ops->eqos_remove_resources(dev);
err_remove_resources_core:
mdio_unregister(eqos->mii);
mdio_free(eqos->mii);
+ eqos->config->ops->eqos_stop_clks(dev);
eqos->config->ops->eqos_remove_resources(dev);
eqos_probe_resources_core(dev);
ret = gpio_request_by_name(dev, "reset-gpios", 0,
&uc_priv->reset_gpio,
GPIOD_IS_OUT);
- if (ret != -ENOENT)
+ if (ret && ret != -ENOENT)
return ret;
uc_priv->reset_assert_delay = dev_read_u32_default(dev, "reset-assert-us", 0);
.clken = MACB_BIT(CLKEN),
};
-static const struct macb_config default_gem_config = {
+static struct macb_config default_gem_config = {
.dma_burst_length = 16,
.hw_dma_cap = HW_DMA_CAP_32B,
.clk_init = NULL,
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
macb->config = (struct macb_config *)dev_get_driver_data(dev);
- if (!macb->config)
+ if (!macb->config) {
+ if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT)) {
+ if (GEM_BFEXT(DAW64, gem_readl(macb, DCFG6)))
+ default_gem_config.hw_dma_cap = HW_DMA_CAP_64B;
+ }
macb->config = &default_gem_config;
+ }
#ifdef CONFIG_CLK
ret = macb_enable_clk(dev);
.clken = BIT(2),
};
-static const struct macb_config microchip_config = {
- .dma_burst_length = 16,
- .hw_dma_cap = HW_DMA_CAP_64B,
- .clk_init = NULL,
- .usrio = &macb_default_usrio,
-};
-
static const struct macb_config sama5d4_config = {
.dma_burst_length = 4,
.hw_dma_cap = HW_DMA_CAP_32B,
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "sifive,fu540-c000-gem",
.data = (ulong)&sifive_config },
- { .compatible = "microchip,mpfs-mss-gem",
- .data = (ulong)µchip_config },
{ }
};
struct phy_device *phydev;
struct mii_dev *bus;
void __iomem *iobase;
- struct clk clk;
+ struct clk_bulk clks;
struct gpio_desc reset_gpio;
};
iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
eth->iobase = iobase;
- ret = clk_get_by_index(dev, 0, ð->clk);
+ ret = clk_get_bulk(dev, ð->clks);
if (ret < 0)
goto err_mdio_alloc;
eth->bus = miiphy_get_dev_by_name(dev->name);
/* Bring up PHY */
- ret = clk_enable(ð->clk);
+ ret = clk_enable_bulk(ð->clks);
if (ret)
goto err_mdio_register;
return 0;
err_mdio_reset:
- clk_disable(ð->clk);
+ clk_release_bulk(ð->clks);
err_mdio_register:
mdio_free(mdiodev);
err_mdio_alloc:
{
struct ravb_priv *eth = dev_get_priv(dev);
- clk_disable(ð->clk);
+ clk_release_bulk(ð->clks);
free(eth->phydev);
mdio_unregister(eth->bus);
int sec_busno;
struct udevice *dev;
struct gpio_desc reset_gpio;
- u32 cfgcache[0x34 - 0x10];
+ u32 cfgcache[(0x3c - 0x10) / 4];
bool cfgcrssve;
};
}
/*
- * The configuration space of the PCI Bridge on primary (local) bus is
+ * The configuration space of the PCI Bridge on primary (first) bus is
* not accessible via PIO transfers like all other PCIe devices. PCI
* Bridge config registers are available directly in Aardvark memory
- * space starting at offset zero. Moreover PCI Bridge registers in the
- * range 0x10 - 0x34 are not available and register 0x38 (Expansion ROM
- * Base Address) is at offset 0x30.
- * We therefore read configuration space content of the primary PCI
- * Bridge from our virtual cache.
+ * space starting at offset zero. The PCI Bridge config space is of
+ * Type 0, but the BAR registers (including ROM BAR) don't have the same
+ * meaning as in the PCIe specification. Therefore do not access BAR
+ * registers and non-common registers (those which have different
+ * meaning for Type 0 and Type 1 config space) of the primary PCI Bridge
+ * and instead read their content from driver virtual cfgcache[].
*/
if (busno == pcie->first_busno) {
- if (offset >= 0x10 && offset < 0x34)
+ if ((offset >= 0x10 && offset < 0x34) || (offset >= 0x38 && offset < 0x3c))
data = pcie->cfgcache[(offset - 0x10) / 4];
- else if ((offset & ~3) == PCI_ROM_ADDRESS1)
- data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
else
data = advk_readl(pcie, offset & ~3);
}
/*
- * As explained in pcie_advk_read_config(), for the configuration
- * space of the primary PCI Bridge, we write the content into virtual
- * cache.
+ * As explained in pcie_advk_read_config(), PCI Bridge config registers
+ * are available directly in Aardvark memory space starting at offset
+ * zero. Type 1 specific registers are not available, so we write their
+ * content only into driver virtual cfgcache[].
*/
if (busno == pcie->first_busno) {
- if (offset >= 0x10 && offset < 0x34) {
+ if ((offset >= 0x10 && offset < 0x34) ||
+ (offset >= 0x38 && offset < 0x3c)) {
data = pcie->cfgcache[(offset - 0x10) / 4];
data = pci_conv_size_to_32(data, value, offset, size);
/* This PCI bridge does not have configurable bars */
if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
- (offset & ~3) == PCI_BASE_ADDRESS_1)
+ (offset & ~3) == PCI_BASE_ADDRESS_1 ||
+ (offset & ~3) == PCI_ROM_ADDRESS1)
data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
- } else if ((offset & ~3) == PCI_ROM_ADDRESS1) {
- data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);
- data = pci_conv_size_to_32(data, value, offset, size);
- advk_writel(pcie, data, PCIE_CORE_EXP_ROM_BAR_REG);
} else {
data = advk_readl(pcie, offset & ~3);
data = pci_conv_size_to_32(data, value, offset, size);
*
* Note that this Aardvark PCI Bridge does not have a compliant Type 1
* Configuration Space and it even cannot be accessed via Aardvark's
- * PCI config space access method. Something like config space is
+ * PCI config space access method. Aardvark PCI Bridge Config space is
* available in internal Aardvark registers starting at offset 0x0
- * and is reported as Type 0. In range 0x10 - 0x34 it has totally
- * different registers. So our driver reports Header Type as Type 1 and
- * for the above mentioned range redirects access to the virtual
- * cfgcache[] buffer, which avoids changing internal Aardvark registers.
+ * and has format of Type 0 config space.
+ *
+ * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
+ * have the same format in Marvell's specification as in PCIe
+ * specification, but their meaning is totally different (and not even
+ * the same meaning as explained in the corresponding comment in the
+ * pci_mvebu driver; aardvark is still different).
+ *
+ * So our driver converts Type 0 config space to Type 1 and reports
+ * Header Type as Type 1. Access to BAR registers and to non-existent
+ * Type 1 registers is redirected to the virtual cfgcache[] buffer,
+ * which avoids changing unrelated registers.
*/
reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
reg &= ~0xffffff00;
unsigned int mem_attr;
unsigned int io_target;
unsigned int io_attr;
- u32 cfgcache[0x34 - 0x10];
+ u32 cfgcache[(0x3c - 0x10) / 4];
};
/*
}
/*
- * mvebu has different internal registers mapped into PCI config space
- * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
- * for this range and instead read content from driver virtual cfgcache
+ * The configuration space of the PCI Bridge on primary (first) bus is
+ * of Type 0 but the BAR registers (including ROM BAR) don't have the
+ * same meaning as in the PCIe specification. Therefore do not access
+ * BAR registers and non-common registers (those which have different
+ * meaning for Type 0 and Type 1 config space) of the PCI Bridge and
+ * instead read their content from driver virtual cfgcache[].
*/
- if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
+ if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
+ (offset >= 0x38 && offset < 0x3c))) {
data = pcie->cfgcache[(offset - 0x10) / 4];
debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n",
offset, size, data);
*valuep = pci_conv_32_to_size(data, offset, size);
return 0;
- } else if (busno == pcie->first_busno &&
- (offset & ~3) == PCI_ROM_ADDRESS1) {
- /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
- offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
}
/*
}
/*
- * mvebu has different internal registers mapped into PCI config space
- * in range 0x10-0x34 for PCI bridge, so do not access PCI config space
- * for this range and instead write content to driver virtual cfgcache
+ * As explained in mvebu_pcie_read_config(), PCI Bridge Type 1 specific
+ * config registers are not available, so we write their content only
+ * into driver virtual cfgcache[].
+ * And as explained in mvebu_pcie_probe(), mvebu has its own specific
+ * way for configuring primary and secondary bus numbers.
*/
- if (busno == pcie->first_busno && offset >= 0x10 && offset < 0x34) {
+ if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) ||
+ (offset >= 0x38 && offset < 0x3c))) {
debug("Writing to cfgcache only\n");
data = pcie->cfgcache[(offset - 0x10) / 4];
data = pci_conv_size_to_32(data, value, offset, size);
/* mvebu PCI bridge does not have configurable bars */
if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
- (offset & ~3) == PCI_BASE_ADDRESS_1)
+ (offset & ~3) == PCI_BASE_ADDRESS_1 ||
+ (offset & ~3) == PCI_ROM_ADDRESS1)
data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
/* mvebu has its own way how to set PCI primary bus number */
pcie->sec_busno);
}
return 0;
- } else if (busno == pcie->first_busno &&
- (offset & ~3) == PCI_ROM_ADDRESS1) {
- /* mvebu has Expansion ROM Base Address (0x38) at offset 0x30 */
- offset -= PCI_ROM_ADDRESS1 - PCIE_EXP_ROM_BAR_OFF;
}
/*
* U-Boot cannot recognize as P2P Bridge.
*
* Note that this mvebu PCI Bridge does not have compliant Type 1
- * Configuration Space. Header Type is reported as Type 0 and in
- * range 0x10-0x34 it has aliased internal mvebu registers 0x10-0x34
- * (e.g. PCIE_BAR_LO_OFF) and register 0x38 is reserved.
+ * Configuration Space. Header Type is reported as Type 0 and it
+ * has format of Type 0 config space.
*
- * Driver for this range redirects access to virtual cfgcache[] buffer
- * which avoids changing internal mvebu registers. And changes Header
- * Type response value to Type 1.
+ * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
+ * have the same format in Marvell's specification as in PCIe
+ * specification, but their meaning is totally different and they do
+ * different things: they are aliased into internal mvebu registers
+ * (e.g. PCIE_BAR_LO_OFF) and these should not be changed or
+ * reconfigured by pci device drivers.
+ *
+ * So our driver converts Type 0 config space to Type 1 and reports
+ * Header Type as Type 1. Access to BAR registers and to non-existent
+ * Type 1 registers is redirected to the virtual cfgcache[] buffer,
+ * which avoids changing unrelated registers.
*/
reg = readl(pcie->base + PCIE_DEV_REV_OFF);
reg &= ~0xffffff00;
The driver implements read/write operations for use with the FAN53555
regulator driver and binds the regulator driver to its node.
+config SPL_DM_PMIC_FAN53555
+ bool "Enable support for OnSemi FAN53555 in SPL"
+ depends on SPL_DM_REGULATOR && SPL_DM_I2C
+ select SPL_DM_REGULATOR_FAN53555
+ help
+ This config enables implementation of driver-model PMIC
+ uclass features for the FAN53555 regulator. The FAN53555 is
+ a (family of) single-output regulators that supports
+ transitioning between two different output voltages based on
+ an voltage selection pin.
+
+ The driver implements read/write operations for use with the FAN53555
+ regulator driver and binds the regulator driver to its node.
+
config DM_PMIC_MP5416
bool "Enable Driver Model for PMIC MP5416"
help
# Lukasz Majewski <l.majewski@samsung.com>
obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o
-obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o
obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
IF_TYPE_SATA,
IF_TYPE_HOST,
IF_TYPE_NVME,
- IF_TYPE_EFI,
+ IF_TYPE_EFI_LOADER,
IF_TYPE_PVBLOCK,
IF_TYPE_VIRTIO,
+ IF_TYPE_EFI_MEDIA,
IF_TYPE_COUNT, /* Number of interface types */
};
lbaint_t lba, struct udevice **devp);
/**
+ * blk_probe_or_unbind() - Try to probe
+ *
+ * Try to probe the device, primarily for enumerating partitions.
+ * If it fails, the device itself is unbound since it means that it won't
+ * work any more.
+ *
+ * @dev: The device to probe
+ * Return: 0 if OK, -ve on error
+ */
+int blk_probe_or_unbind(struct udevice *dev);
+
+/**
* blk_unbind_all() - Unbind all device of the given interface type
*
* The devices are removed and then unbound.
*
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
- * @return clock rate in Hz, or -ve error code.
+ * @return clock rate in Hz on success, 0 for invalid clock, or -ve error code
+ * for other errors.
*/
ulong clk_get_rate(struct clk *clk);
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+/* Support autoboot from RAM (kernel image is loaded via debug port) */
+#define KERNEL_IMAGE_ADDR "0x2000000 "
+#define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \
+ "ram "
+#define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \
+ "bootcmd_ram=" \
+ "booti " \
+ KERNEL_IMAGE_ADDR \
+ "- $fdtcontroladdr\0"
+
/* When we use RAM as ENV */
/* Enable distro boot */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
- func(DHCP, dhcp, na)
+ func(DHCP, dhcp, na) \
+ func(RAM, ram, na)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
"boot_fdt=try\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
- "mmcdev=0\0" \
+ "mmcdev=1\0" \
"mmcpart=1\0" \
"mmcrootpart=2\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \
#define CONFIG_IRAM_BASE 0xfdcc0000
#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
+
+#define CONFIG_SPL_STACK 0x00400000
+#define CONFIG_SPL_MAX_SIZE 0x20000
+#define CONFIG_SPL_BSS_START_ADDR 0x4000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x4000
+
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define CONFIG_SYS_SDRAM_BASE 0
#if CONFIG_IS_ENABLED(CMD_MMC)
#define BOOT_TARGET_MMC(func) \
func(MMC, mmc, 0) \
- func(MMC, mmc, 1)
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2)
#else
#define BOOT_TARGET_MMC(func)
#endif
"env_check=if env info -p -d -q; then env save; fi\0" \
"boot_net_usb_start=true\0"
+#ifndef STM32MP_BOARD_EXTRA_ENV
+#define STM32MP_BOARD_EXTRA_ENV
+#endif
+
#include <config_distro_bootcmd.h>
/*
STM32MP_BOOTCMD \
STM32MP_PARTS_DEFAULT \
BOOTENV \
- STM32MP_EXTRA
+ STM32MP_EXTRA \
+ STM32MP_BOARD_EXTRA_ENV
#endif /* ifndef CONFIG_SPL_BUILD */
#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
#ifndef __CONFIG_STM32MP15_DH_DHSOM_H__
#define __CONFIG_STM32MP15_DH_DHSOM_H__
+/* PHY needs a longer autoneg timeout */
+#define PHY_ANEG_TIMEOUT 20000
+
+#define STM32MP_BOARD_EXTRA_ENV \
+ "usb_pgood_delay=1000\0" \
+ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
+ "setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \
+ "load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && " \
+ "env set filesize1 ${filesize} && " \
+ "load mmc 0:4 ${loadaddr} /boot/u-boot.itb && " \
+ "sf probe && sf erase 0 0x200000 && " \
+ "sf update ${loadaddr1} 0 ${filesize1} && " \
+ "sf update ${loadaddr1} 0x40000 ${filesize1} && " \
+ "sf update ${loadaddr} 0x80000 ${filesize} && " \
+ "env set filesize1 && env set loadaddr1\0"
+
#include <configs/stm32mp15_common.h>
#define CONFIG_SPL_TARGET "u-boot.itb"
* @parent: parent device to scan
*/
#define device_foreach_child_of_to_plat(pos, parent) \
- for (int _ret = device_first_child_ofdata_err(parent, &dev); !_ret; \
- _ret = device_next_child_ofdata_err(&dev))
+ for (int _ret = device_first_child_ofdata_err(parent, &pos); !_ret; \
+ _ret = device_next_child_ofdata_err(&pos))
/**
* device_foreach_child_probe() - iterate through children, probing them
* @parent: parent device to scan
*/
#define device_foreach_child_probe(pos, parent) \
- for (int _ret = device_first_child_err(parent, &dev); !_ret; \
- _ret = device_next_child_err(&dev))
+ for (int _ret = device_first_child_err(parent, &pos); !_ret; \
+ _ret = device_next_child_err(&pos))
/**
* dm_scan_fdt_dev() - Bind child device in the device tree
UCLASS_DMA, /* Direct Memory Access */
UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */
UCLASS_ECDSA, /* Elliptic curve cryptographic device */
- UCLASS_EFI, /* EFI managed devices */
+ UCLASS_EFI_LOADER, /* Devices created by UEFI applications */
+ UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
UCLASS_FIRMWARE, /* Firmware */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
+
+#define PLIC_INT_INVALID 0
+#define PLIC_INT_L2_METADATA_CORR 1
+#define PLIC_INT_L2_METADATA_UNCORR 2
+#define PLIC_INT_L2_DATA_CORR 3
+#define PLIC_INT_L2_DATA_UNCORR 4
+#define PLIC_INT_DMA_CH0_DONE 5
+#define PLIC_INT_DMA_CH0_ERR 6
+#define PLIC_INT_DMA_CH1_DONE 7
+#define PLIC_INT_DMA_CH1_ERR 8
+#define PLIC_INT_DMA_CH2_DONE 9
+#define PLIC_INT_DMA_CH2_ERR 10
+#define PLIC_INT_DMA_CH3_DONE 11
+#define PLIC_INT_DMA_CH3_ERR 12
+
+#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13
+#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14
+#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15
+#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16
+#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17
+#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18
+#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19
+#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20
+#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21
+#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22
+#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23
+#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24
+#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25
+#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26
+#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27
+#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28
+#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29
+#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30
+#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31
+#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32
+#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33
+#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34
+#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35
+#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36
+#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37
+#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38
+#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39
+#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40
+#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41
+#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42
+#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43
+#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44
+#define PLIC_INT_GPIO1_BIT18 45
+#define PLIC_INT_GPIO1_BIT19 46
+#define PLIC_INT_GPIO1_BIT20 47
+#define PLIC_INT_GPIO1_BIT21 48
+#define PLIC_INT_GPIO1_BIT22 49
+#define PLIC_INT_GPIO1_BIT23 50
+#define PLIC_INT_GPIO0_NON_DIRECT 51
+#define PLIC_INT_GPIO1_NON_DIRECT 52
+#define PLIC_INT_GPIO2_NON_DIRECT 53
+#define PLIC_INT_SPI0 54
+#define PLIC_INT_SPI1 55
+#define PLIC_INT_CAN0 56
+#define PLIC_INT_CAN1 57
+#define PLIC_INT_I2C0_MAIN 58
+#define PLIC_INT_I2C0_ALERT 59
+#define PLIC_INT_I2C0_SUS 60
+#define PLIC_INT_I2C1_MAIN 61
+#define PLIC_INT_I2C1_ALERT 62
+#define PLIC_INT_I2C1_SUS 63
+#define PLIC_INT_MAC0_INT 64
+#define PLIC_INT_MAC0_QUEUE1 65
+#define PLIC_INT_MAC0_QUEUE2 66
+#define PLIC_INT_MAC0_QUEUE3 67
+#define PLIC_INT_MAC0_EMAC 68
+#define PLIC_INT_MAC0_MMSL 69
+#define PLIC_INT_MAC1_INT 70
+#define PLIC_INT_MAC1_QUEUE1 71
+#define PLIC_INT_MAC1_QUEUE2 72
+#define PLIC_INT_MAC1_QUEUE3 73
+#define PLIC_INT_MAC1_EMAC 74
+#define PLIC_INT_MAC1_MMSL 75
+#define PLIC_INT_DDRC_TRAIN 76
+#define PLIC_INT_SCB_INTERRUPT 77
+#define PLIC_INT_ECC_ERROR 78
+#define PLIC_INT_ECC_CORRECT 79
+#define PLIC_INT_RTC_WAKEUP 80
+#define PLIC_INT_RTC_MATCH 81
+#define PLIC_INT_TIMER1 82
+#define PLIC_INT_TIMER2 83
+#define PLIC_INT_ENVM 84
+#define PLIC_INT_QSPI 85
+#define PLIC_INT_USB_DMA 86
+#define PLIC_INT_USB_MC 87
+#define PLIC_INT_MMC_MAIN 88
+#define PLIC_INT_MMC_WAKEUP 89
+#define PLIC_INT_MMUART0 90
+#define PLIC_INT_MMUART1 91
+#define PLIC_INT_MMUART2 92
+#define PLIC_INT_MMUART3 93
+#define PLIC_INT_MMUART4 94
+#define PLIC_INT_G5C_DEVRST 95
+#define PLIC_INT_G5C_MESSAGE 96
+#define PLIC_INT_USOC_VC_INTERRUPT 97
+#define PLIC_INT_USOC_SMB_INTERRUPT 98
+#define PLIC_INT_E51_0_MAINTENACE 99
+#define PLIC_INT_WDOG0_MRVP 100
+#define PLIC_INT_WDOG1_MRVP 101
+#define PLIC_INT_WDOG2_MRVP 102
+#define PLIC_INT_WDOG3_MRVP 103
+#define PLIC_INT_WDOG4_MRVP 104
+#define PLIC_INT_WDOG0_TOUT 105
+#define PLIC_INT_WDOG1_TOUT 106
+#define PLIC_INT_WDOG2_TOUT 107
+#define PLIC_INT_WDOG3_TOUT 108
+#define PLIC_INT_WDOG4_TOUT 109
+#define PLIC_INT_G5C_MSS_SPI 110
+#define PLIC_INT_VOLT_TEMP_ALARM 111
+#define PLIC_INT_ATHENA_COMPLETE 112
+#define PLIC_INT_ATHENA_ALARM 113
+#define PLIC_INT_ATHENA_BUS_ERROR 114
+#define PLIC_INT_USOC_AXIC_US 115
+#define PLIC_INT_USOC_AXIC_DS 116
+#define PLIC_INT_SPARE 117
+#define PLIC_INT_FABRIC_F2H_0 118
+#define PLIC_INT_FABRIC_F2H_1 119
+#define PLIC_INT_FABRIC_F2H_2 120
+#define PLIC_INT_FABRIC_F2H_3 121
+#define PLIC_INT_FABRIC_F2H_4 122
+#define PLIC_INT_FABRIC_F2H_5 123
+#define PLIC_INT_FABRIC_F2H_6 124
+#define PLIC_INT_FABRIC_F2H_7 125
+#define PLIC_INT_FABRIC_F2H_8 126
+#define PLIC_INT_FABRIC_F2H_9 127
+#define PLIC_INT_FABRIC_F2H_10 128
+#define PLIC_INT_FABRIC_F2H_11 129
+#define PLIC_INT_FABRIC_F2H_12 130
+#define PLIC_INT_FABRIC_F2H_13 131
+#define PLIC_INT_FABRIC_F2H_14 132
+#define PLIC_INT_FABRIC_F2H_15 133
+#define PLIC_INT_FABRIC_F2H_16 134
+#define PLIC_INT_FABRIC_F2H_17 135
+#define PLIC_INT_FABRIC_F2H_18 136
+#define PLIC_INT_FABRIC_F2H_19 137
+#define PLIC_INT_FABRIC_F2H_20 138
+#define PLIC_INT_FABRIC_F2H_21 139
+#define PLIC_INT_FABRIC_F2H_22 140
+#define PLIC_INT_FABRIC_F2H_23 141
+#define PLIC_INT_FABRIC_F2H_24 142
+#define PLIC_INT_FABRIC_F2H_25 143
+#define PLIC_INT_FABRIC_F2H_26 144
+#define PLIC_INT_FABRIC_F2H_27 145
+#define PLIC_INT_FABRIC_F2H_28 146
+#define PLIC_INT_FABRIC_F2H_29 147
+#define PLIC_INT_FABRIC_F2H_30 148
+#define PLIC_INT_FABRIC_F2H_31 149
+#define PLIC_INT_FABRIC_F2H_32 150
+#define PLIC_INT_FABRIC_F2H_33 151
+#define PLIC_INT_FABRIC_F2H_34 152
+#define PLIC_INT_FABRIC_F2H_35 153
+#define PLIC_INT_FABRIC_F2H_36 154
+#define PLIC_INT_FABRIC_F2H_37 155
+#define PLIC_INT_FABRIC_F2H_38 156
+#define PLIC_INT_FABRIC_F2H_39 157
+#define PLIC_INT_FABRIC_F2H_40 158
+#define PLIC_INT_FABRIC_F2H_41 159
+#define PLIC_INT_FABRIC_F2H_42 160
+#define PLIC_INT_FABRIC_F2H_43 161
+#define PLIC_INT_FABRIC_F2H_44 162
+#define PLIC_INT_FABRIC_F2H_45 163
+#define PLIC_INT_FABRIC_F2H_46 164
+#define PLIC_INT_FABRIC_F2H_47 165
+#define PLIC_INT_FABRIC_F2H_48 166
+#define PLIC_INT_FABRIC_F2H_49 167
+#define PLIC_INT_FABRIC_F2H_50 168
+#define PLIC_INT_FABRIC_F2H_51 169
+#define PLIC_INT_FABRIC_F2H_52 170
+#define PLIC_INT_FABRIC_F2H_53 171
+#define PLIC_INT_FABRIC_F2H_54 172
+#define PLIC_INT_FABRIC_F2H_55 173
+#define PLIC_INT_FABRIC_F2H_56 174
+#define PLIC_INT_FABRIC_F2H_57 175
+#define PLIC_INT_FABRIC_F2H_58 176
+#define PLIC_INT_FABRIC_F2H_59 177
+#define PLIC_INT_FABRIC_F2H_60 178
+#define PLIC_INT_FABRIC_F2H_61 179
+#define PLIC_INT_FABRIC_F2H_62 180
+#define PLIC_INT_FABRIC_F2H_63 181
+#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182
+#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183
+#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184
+#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185
+#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186
+
+#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
+
+#define HART_INT_U_SOFT 0
+#define HART_INT_S_SOFT 1
+#define HART_INT_M_SOFT 3
+#define HART_INT_U_TIMER 4
+#define HART_INT_S_TIMER 5
+#define HART_INT_M_TIMER 7
+#define HART_INT_U_EXT 8
+#define HART_INT_S_EXT 9
+#define HART_INT_M_EXT 11
+
+#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
void *next_hdr;
};
+/*
+ * EFI attributes of the udevice handled by efi_media driver
+ *
+ * @handle: handle of the controller on which this driver is installed
+ * @blkio: block io protocol proxied by this driver
+ */
+struct efi_media_plat {
+ efi_handle_t handle;
+ struct efi_block_io *blkio;
+};
+
/* Base address of the EFI image */
extern char image_base[];
efi_status_t efi_rng_register(void);
/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
efi_status_t efi_tcg2_register(void);
+/* Called by efi_init_obj_list() to do initial measurement */
+efi_status_t efi_tcg2_do_initial_measurement(void);
/* measure the pe-coff image, extend PCR and add Event Log */
efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
struct efi_loaded_image_obj *handle,
if (!obj)
return -ENOENT;
- devnum = blk_find_max_devnum(IF_TYPE_EFI);
+ devnum = blk_find_max_devnum(IF_TYPE_EFI_LOADER);
if (devnum == -ENODEV)
devnum = 0;
else if (devnum < 0)
sprintf(name, "efiblk#%d", devnum);
/* Create driver model udevice for the EFI block io device */
- ret = blk_create_device(parent, "efi_blk", name, IF_TYPE_EFI, devnum,
- io->media->block_size,
+ ret = blk_create_device(parent, "efi_blk", name, IF_TYPE_EFI_LOADER,
+ devnum, io->media->block_size,
(lbaint_t)io->media->last_block, &bdev);
if (ret)
return ret;
/* Identify as EFI driver */
U_BOOT_DRIVER(efi_block) = {
.name = "EFI block driver",
- .id = UCLASS_EFI,
+ .id = UCLASS_EFI_LOADER,
.ops = &driver_ops,
};
log_debug("Initializing EFI driver framework\n");
for (drv = ll_entry_start(struct driver, driver);
drv < ll_entry_end(struct driver, driver); ++drv) {
- if (drv->id == UCLASS_EFI) {
+ if (drv->id == UCLASS_EFI_LOADER) {
ret = efi_add_driver(drv);
if (ret != EFI_SUCCESS) {
log_err("Failed to add EFI driver %s\n",
*/
static int efi_uc_init(struct uclass *class)
{
- log_debug("Initializing UCLASS_EFI\n");
+ log_debug("Initializing UCLASS_EFI_LOADER\n");
return 0;
}
*/
static int efi_uc_destroy(struct uclass *class)
{
- log_debug("Destroying UCLASS_EFI\n");
+ log_debug("Destroying UCLASS_EFI_LOADER\n");
return 0;
}
UCLASS_DRIVER(efi) = {
.name = "efi",
- .id = UCLASS_EFI,
+ .id = UCLASS_EFI_LOADER,
.init = efi_uc_init,
.destroy = efi_uc_destroy,
};
bool "EFI_TCG2_PROTOCOL support"
default y
depends on TPM_V2
+ # Sandbox TPM currently fails on GetCapabilities needed for TCG2
+ depends on !SANDBOX
select SHA1
select SHA256
select SHA384
if (IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL)) {
if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION) {
ret = efi_tcg2_measure_efi_app_invocation(image_obj);
- if (ret != EFI_SUCCESS) {
- log_warning("tcg2 measurement fails(0x%lx)\n",
- ret);
+ if (ret == EFI_SECURITY_VIOLATION) {
+ /*
+ * TCG2 Protocol is installed but no TPM device found,
+ * this is not expected.
+ */
+ return EFI_EXIT(EFI_SECURITY_VIOLATION);
}
}
}
#if CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL)
/* Measure an PE/COFF image */
- if (tcg2_measure_pe_image(efi, efi_size, handle,
- loaded_image_info))
- log_err("PE image measurement failed\n");
+ ret = tcg2_measure_pe_image(efi, efi_size, handle, loaded_image_info);
+ if (ret == EFI_SECURITY_VIOLATION) {
+ /*
+ * TCG2 Protocol is installed but no TPM device found,
+ * this is not expected.
+ */
+ log_err("PE image measurement failed, no tpm device found\n");
+ goto err;
+ }
+
#endif
/* Copy PE headers */
ret = efi_tcg2_register();
if (ret != EFI_SUCCESS)
goto out;
+
+ ret = efi_tcg2_do_initial_measurement();
+ if (ret == EFI_SECURITY_VIOLATION)
+ goto out;
}
/* Secure boot */
return 0;
}
+static bool is_tcg2_protocol_installed(void)
+{
+ struct efi_handler *handler;
+ efi_status_t ret;
+
+ ret = efi_search_protocol(efi_root, &efi_guid_tcg2_protocol, &handler);
+ return ret == EFI_SUCCESS;
+}
+
static u32 tcg_event_final_size(struct tpml_digest_values *digest_list)
{
u32 len;
IMAGE_NT_HEADERS32 *nt;
struct efi_handler *handler;
+ if (!is_tcg2_protocol_installed())
+ return EFI_SUCCESS;
+
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS)
- return ret;
+ return EFI_SECURITY_VIOLATION;
switch (handle->image_type) {
case IMAGE_SUBSYSTEM_EFI_APPLICATION:
event_log.buffer = NULL;
efi_free_pool(event_log.final_buffer);
event_log.final_buffer = NULL;
+
+ if (!is_tcg2_protocol_installed())
+ return;
+
+ ret = efi_remove_protocol(efi_root, &efi_guid_tcg2_protocol,
+ (void *)&efi_tcg2_protocol);
+ if (ret != EFI_SUCCESS)
+ log_err("Failed to remove EFI TCG2 protocol\n");
}
/**
u32 event = 0;
struct smbios_entry *entry;
+ if (!is_tcg2_protocol_installed())
+ return EFI_SUCCESS;
+
if (tcg2_efi_app_invoked)
return EFI_SUCCESS;
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS)
- return ret;
+ return EFI_SECURITY_VIOLATION;
ret = tcg2_measure_boot_variable(dev);
if (ret != EFI_SUCCESS)
efi_status_t ret;
struct udevice *dev;
+ if (!is_tcg2_protocol_installed())
+ return EFI_SUCCESS;
+
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS)
return ret;
EFI_ENTRY("%p, %p", event, context);
event_log.ebs_called = true;
+
+ if (!is_tcg2_protocol_installed()) {
+ ret = EFI_SUCCESS;
+ goto out;
+ }
+
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS)
goto out;
struct udevice *dev;
efi_status_t ret;
+ if (!is_tcg2_protocol_installed())
+ return EFI_SUCCESS;
+
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS)
goto out;
}
/**
+ * efi_tcg2_do_initial_measurement() - do initial measurement
+ *
+ * Return: status code
+ */
+efi_status_t efi_tcg2_do_initial_measurement(void)
+{
+ efi_status_t ret;
+ struct udevice *dev;
+
+ if (!is_tcg2_protocol_installed())
+ return EFI_SUCCESS;
+
+ ret = platform_get_tpm2_device(&dev);
+ if (ret != EFI_SUCCESS)
+ return EFI_SECURITY_VIOLATION;
+
+ ret = tcg2_measure_secure_boot_variable(dev);
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+out:
+ return ret;
+}
+
+/**
* efi_tcg2_register() - register EFI_TCG2_PROTOCOL
*
* If a TPM2 device is available, the TPM TCG2 Protocol is registered
*
- * Return: An error status is only returned if adding the protocol fails.
+ * Return: status code
*/
efi_status_t efi_tcg2_register(void)
{
}
ret = efi_init_event_log();
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS) {
+ tcg2_uninit();
goto fail;
+ }
ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol,
(void *)&efi_tcg2_protocol);
goto fail;
}
- ret = tcg2_measure_secure_boot_variable(dev);
- if (ret != EFI_SUCCESS) {
- tcg2_uninit();
- goto fail;
- }
-
return ret;
fail:
log_err("Cannot install EFI_TCG2_PROTOCOL\n");
- /*
- * Return EFI_SUCCESS and don't stop the EFI subsystem.
- * That's done for 2 reasons
- * - If the protocol is not installed the PCRs won't be extended. So
- * someone later in the boot flow will notice that and take the
- * necessary actions.
- * - The TPM sandbox is limited and we won't be able to run any efi
- * related tests with TCG2 enabled
- */
- return EFI_SUCCESS;
+ return ret;
}
obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o
obj-$(CONFIG_DM_DSA) += dsa.o
obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o
+obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o
obj-$(CONFIG_DM_ETH) += eth.o
ifneq ($(CONFIG_EFI_PARTITION),)
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for EFI_MEDIA uclass
+ *
+ * Copyright 2021 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* Test that we can use the EFI_MEDIA uclass */
+static int dm_test_efi_media(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_first_device_err(UCLASS_EFI_MEDIA, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_efi_media, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
}
erase.length = erasesize;
- if (DEVTYPE(dev) != MTD_ABSENT) {
- was_locked = ioctl(fd, MEMISLOCKED, &erase);
- /* treat any errors as unlocked flash */
- if (was_locked < 0)
- was_locked = 0;
- }
/* This only runs once on NOR flash and SPI-dataflash */
while (processed < write_total) {
if (DEVTYPE(dev) != MTD_ABSENT) {
erase.start = blockstart;
+ was_locked = ioctl(fd, MEMISLOCKED, &erase);
+ /* treat any errors as unlocked flash */
+ if (was_locked < 0)
+ was_locked = 0;
if (was_locked)
ioctl(fd, MEMUNLOCK, &erase);
/* These do not need an explicit erase cycle */
char tmp = ENV_REDUND_OBSOLETE;
int was_locked; /* flash lock flag */
- was_locked = ioctl(fd, MEMISLOCKED, &erase);
erase.start = DEVOFFSET(dev);
erase.length = DEVESIZE(dev);
/* This relies on the fact, that ENV_REDUND_OBSOLETE == 0 */
DEVNAME(dev));
return rc;
}
+ was_locked = ioctl(fd, MEMISLOCKED, &erase);
+ /* treat any errors as unlocked flash */
+ if (was_locked < 0)
+ was_locked = 0;
if (was_locked)
ioctl(fd, MEMUNLOCK, &erase);
rc = write(fd, &tmp, sizeof(tmp));
#include "imagetool.h"
#include <image.h>
+#include <u-boot/sha256.h>
#include <rc4.h>
#include "mkimage.h"
#include "rkcommon.h"
enum {
- RK_SIGNATURE = 0x0ff0aa55,
+ RK_MAGIC = 0x0ff0aa55,
+ RK_MAGIC_V2 = 0x534E4B52,
+};
+
+enum {
+ RK_HEADER_V1 = 1,
+ RK_HEADER_V2 = 2,
+};
+
+enum hash_type {
+ HASH_NONE = 0,
+ HASH_SHA256 = 1,
+ HASH_SHA512 = 2,
+};
+
+/**
+ * struct image_entry
+ *
+ * @size_and_off: [31:16]image size;[15:0]image offset
+ * @address: default as 0xFFFFFFFF
+ * @flag: no use
+ * @counter: no use
+ * @hash: hash of image
+ *
+ */
+struct image_entry {
+ uint32_t size_and_off;
+ uint32_t address;
+ uint32_t flag;
+ uint32_t counter;
+ uint8_t reserved[8];
+ uint8_t hash[64];
+};
+
+/**
+ * struct header0_info_v2 - v2 header block for rockchip BootRom
+ *
+ * This is stored at SD card block 64 (where each block is 512 bytes)
+ *
+ * @magic: Magic (must be RK_MAGIC_V2)
+ * @size_and_nimage: [31:16]number of images;[15:0]
+ * offset to hash field of header(unit as 4Byte)
+ * @boot_flag: [3:0]hash type(0:none,1:sha256,2:sha512)
+ * @signature: hash or signature for header info
+ *
+ */
+struct header0_info_v2 {
+ uint32_t magic;
+ uint8_t reserved[4];
+ uint32_t size_and_nimage;
+ uint32_t boot_flag;
+ uint8_t reserved1[104];
+ struct image_entry images[4];
+ uint8_t reserved2[1064];
+ uint8_t hash[512];
};
/**
* This is stored at SD card block 64 (where each block is 512 bytes, or at
* the start of SPI flash. It is encoded with RC4.
*
- * @signature: Signature (must be RKSD_SIGNATURE)
+ * @magic: Magic (must be RK_MAGIC)
* @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary
* @init_offset: Offset in blocks of the SPL code from this header
* block. E.g. 4 means 2KB after the start of this header.
* Other fields are not used by U-Boot
*/
struct header0_info {
- uint32_t signature;
+ uint32_t magic;
uint8_t reserved[4];
uint32_t disable_rc4;
uint16_t init_offset;
* @spl_hdr: Boot ROM requires a 4-bytes spl header
* @spl_size: Spl size(include extra 4-bytes spl header)
* @spl_rc4: RC4 encode the SPL binary (same key as header)
+ * @header_ver: header block version
*/
-
struct spl_info {
const char *imagename;
const char *spl_hdr;
const uint32_t spl_size;
const bool spl_rc4;
+ const uint32_t header_ver;
};
static struct spl_info spl_infos[] = {
- { "px30", "RK33", 0x2800, false },
- { "rk3036", "RK30", 0x1000, false },
- { "rk3128", "RK31", 0x1800, false },
- { "rk3188", "RK31", 0x8000 - 0x800, true },
- { "rk322x", "RK32", 0x8000 - 0x1000, false },
- { "rk3288", "RK32", 0x8000, false },
- { "rk3308", "RK33", 0x40000 - 0x1000, false},
- { "rk3328", "RK32", 0x8000 - 0x1000, false },
- { "rk3368", "RK33", 0x8000 - 0x1000, false },
- { "rk3399", "RK33", 0x30000 - 0x2000, false },
- { "rv1108", "RK11", 0x1800, false },
+ { "px30", "RK33", 0x2800, false, RK_HEADER_V1 },
+ { "rk3036", "RK30", 0x1000, false, RK_HEADER_V1 },
+ { "rk3128", "RK31", 0x1800, false, RK_HEADER_V1 },
+ { "rk3188", "RK31", 0x8000 - 0x800, true, RK_HEADER_V1 },
+ { "rk322x", "RK32", 0x8000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3288", "RK32", 0x8000, false, RK_HEADER_V1 },
+ { "rk3308", "RK33", 0x40000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3328", "RK32", 0x8000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3368", "RK33", 0x8000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
+ { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
+ { "rk3568", "RK35", 0x14000 - 0x1000, false, RK_HEADER_V2 },
};
/**
return info->spl_hdr;
}
-
int rkcommon_get_spl_size(struct image_tool_params *params)
{
struct spl_info *info = rkcommon_get_spl_info(params->imagename);
return info->spl_rc4;
}
+bool rkcommon_is_header_v2(struct image_tool_params *params)
+{
+ struct spl_info *info = rkcommon_get_spl_info(params->imagename);
+
+ return (info->header_ver == RK_HEADER_V2);
+}
+
+static void do_sha256_hash(uint8_t *buf, uint32_t size, uint8_t *out)
+{
+ sha256_context ctx;
+
+ sha256_starts(&ctx);
+ sha256_update(&ctx, buf, size);
+ sha256_finish(&ctx, out);
+}
+
static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
{
struct header0_info *hdr = buf;
uint32_t init_boot_size;
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
- hdr->signature = cpu_to_le32(RK_SIGNATURE);
+ hdr->magic = cpu_to_le32(RK_MAGIC);
hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params));
hdr->init_offset = cpu_to_le16(RK_INIT_OFFSET);
hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE);
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
}
+static void rkcommon_set_header0_v2(void *buf, struct image_tool_params *params)
+{
+ struct header0_info_v2 *hdr = buf;
+ uint32_t sector_offset, image_sector_count;
+ uint32_t image_size_array[2];
+ uint8_t *image_ptr = NULL;
+ int i;
+
+ printf("Image Type: Rockchip %s boot image\n",
+ rkcommon_get_spl_hdr(params));
+ memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
+ hdr->magic = cpu_to_le32(RK_MAGIC_V2);
+ hdr->size_and_nimage = cpu_to_le32((2 << 16) + 384);
+ hdr->boot_flag = cpu_to_le32(HASH_SHA256);
+ sector_offset = 4;
+ image_size_array[0] = spl_params.init_size;
+ image_size_array[1] = spl_params.boot_size;
+
+ for (i = 0; i < 2; i++) {
+ image_sector_count = image_size_array[i] / RK_BLK_SIZE;
+ hdr->images[i].size_and_off = cpu_to_le32((image_sector_count
+ << 16) + sector_offset);
+ hdr->images[i].address = 0xFFFFFFFF;
+ hdr->images[i].counter = cpu_to_le32(i + 1);
+ image_ptr = buf + sector_offset * RK_BLK_SIZE;
+ do_sha256_hash(image_ptr, image_size_array[i],
+ hdr->images[i].hash);
+ sector_offset = sector_offset + image_sector_count;
+ }
+
+ do_sha256_hash(buf, (void *)hdr->hash - buf, hdr->hash);
+}
+
void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
struct header1_info *hdr = buf + RK_SPL_HDR_START;
- rkcommon_set_header0(buf, params);
-
- /* Set up the SPL name (i.e. copy spl_hdr over) */
- memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
+ if (rkcommon_is_header_v2(params)) {
+ rkcommon_set_header0_v2(buf, params);
+ } else {
+ rkcommon_set_header0(buf, params);
- if (rkcommon_need_rc4_spl(params))
- rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START,
- spl_params.init_size);
+ /* Set up the SPL name (i.e. copy spl_hdr over) */
+ if (memcmp(&hdr->magic, "RSAK", 4))
+ memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
- if (spl_params.boot_file) {
if (rkcommon_need_rc4_spl(params))
- rkcommon_rc4_encode_spl(buf + RK_SPL_HDR_START,
- spl_params.init_size,
- spl_params.boot_size);
+ rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START,
+ spl_params.init_size);
+
+ if (spl_params.boot_file) {
+ if (rkcommon_need_rc4_spl(params))
+ rkcommon_rc4_encode_spl(buf + RK_SPL_HDR_START,
+ spl_params.init_size,
+ spl_params.boot_size);
+ }
}
}
-static inline unsigned rkcommon_offset_to_spi(unsigned offset)
+static inline unsigned int rkcommon_offset_to_spi(unsigned int offset)
{
/*
* While SD/MMC images use a flat addressing, SPI images are padded
static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
struct spl_info **spl_info)
{
- unsigned hdr1_offset;
+ unsigned int hdr1_offset;
struct header1_info *hdr1_sdmmc, *hdr1_spi;
int i;
memcpy((void *)header0, buf, sizeof(struct header0_info));
rc4_encode((void *)header0, sizeof(struct header0_info), rc4_key);
- if (le32_to_cpu(header0->signature) != RK_SIGNATURE)
+ if (le32_to_cpu(header0->magic) != RK_MAGIC)
return -EPROTO;
/* We don't support RC4 encoded image payloads here, yet... */
return -1;
}
+static int rkcommon_parse_header_v2(const void *buf, struct header0_info_v2 *header)
+{
+ memcpy((void *)header, buf, sizeof(struct header0_info_v2));
+
+ if (le32_to_cpu(header->magic) != RK_MAGIC_V2)
+ return -EPROTO;
+
+ return 0;
+}
+
int rkcommon_verify_header(unsigned char *buf, int size,
struct image_tool_params *params)
{
void rkcommon_print_header(const void *buf)
{
struct header0_info header0;
+ struct header0_info_v2 header0_v2;
struct spl_info *spl_info;
uint8_t image_type;
int ret, boot_size, init_size;
- ret = rkcommon_parse_header(buf, &header0, &spl_info);
+ if ((*(uint32_t *)buf) == RK_MAGIC_V2) {
+ ret = rkcommon_parse_header_v2(buf, &header0_v2);
- /* If this is the (unimplemented) RC4 case, then fail silently */
- if (ret == -ENOSYS)
- return;
+ if (ret < 0) {
+ fprintf(stderr, "Error: image verification failed\n");
+ return;
+ }
- if (ret < 0) {
- fprintf(stderr, "Error: image verification failed\n");
- return;
- }
+ init_size = header0_v2.images[0].size_and_off >> 16;
+ init_size = init_size * RK_BLK_SIZE;
+ boot_size = header0_v2.images[1].size_and_off >> 16;
+ boot_size = boot_size * RK_BLK_SIZE;
+ } else {
+ ret = rkcommon_parse_header(buf, &header0, &spl_info);
- image_type = ret;
+ /* If this is the (unimplemented) RC4 case, then fail silently */
+ if (ret == -ENOSYS)
+ return;
+
+ if (ret < 0) {
+ fprintf(stderr, "Error: image verification failed\n");
+ return;
+ }
+
+ image_type = ret;
+ init_size = header0.init_size * RK_BLK_SIZE;
+ boot_size = header0.init_boot_size * RK_BLK_SIZE - init_size;
+
+ printf("Image Type: Rockchip %s (%s) boot image\n",
+ spl_info->spl_hdr,
+ (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI");
+ }
- printf("Image Type: Rockchip %s (%s) boot image\n",
- spl_info->spl_hdr,
- (image_type == IH_TYPE_RKSD) ? "SD/MMC" : "SPI");
- init_size = le16_to_cpu(header0.init_size) * RK_BLK_SIZE;
printf("Init Data Size: %d bytes\n", init_size);
- boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE - init_size;
if (boot_size != RK_MAX_BOOT_SIZE)
printf("Boot Data Size: %d bytes\n", boot_size);
}
projects / platform / kernel / u-boot.git / commitdiff