arm: at91: pmc: replace the constant with a define in at91_pmc.h
authorErik van Luijk <evanluijk@interact.nl>
Thu, 13 Aug 2015 13:43:20 +0000 (15:43 +0200)
committerAndreas Bießmann <andreas.devel@googlemail.com>
Fri, 21 Aug 2015 13:47:03 +0000 (15:47 +0200)
To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 <<  2).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
arch/arm/mach-at91/include/mach/at91_pmc.h
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/atmel/at91sam9n12ek/at91sam9n12ek.c
board/atmel/at91sam9x5ek/at91sam9x5ek.c
board/atmel/sama5d3_xplained/sama5d3_xplained.c
board/atmel/sama5d3xek/sama5d3xek.c
board/atmel/sama5d4_xplained/sama5d4_xplained.c
board/atmel/sama5d4ek/sama5d4ek.c
board/siemens/corvus/board.c

index ebb7dec..8a3fb94 100644 (file)
@@ -158,6 +158,7 @@ typedef struct at91_pmc {
 
 #define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define                AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
+#define                AT91_PMC_DDR            (1 <<  2)               /* DDR Clock */
 #define                AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
 #define                AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define                AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
index d2ade4d..2fea56f 100644 (file)
@@ -136,7 +136,7 @@ void mem_init(void)
        ddr2_conf(&ddr2);
 
        /* enable DDR2 clock */
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* DDRAM2 Controller initialize */
        ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
index 8437f37..59bc535 100644 (file)
@@ -316,7 +316,7 @@ void mem_init(void)
        ddr2_conf(&ddr2);
 
        /* enable DDR2 clock */
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* Chip select 1 is for DDR2/SDRAM */
        csa = readl(&matrix->ebicsa);
index 0455e2c..1738a2b 100644 (file)
@@ -353,7 +353,7 @@ void mem_init(void)
        ddr2_conf(&ddr2);
 
        /* enable DDR2 clock */
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* Chip select 1 is for DDR2/SDRAM */
        csa = readl(&matrix->ebicsa);
index 0793e4a..7a01149 100644 (file)
@@ -191,7 +191,7 @@ void mem_init(void)
 
        /* enable MPDDR clock */
        at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* DDRAM2 Controller initialize */
        ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
index d6e7e16..2bd436a 100644 (file)
@@ -430,7 +430,7 @@ void mem_init(void)
 
        /* enable MPDDR clock */
        at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* DDRAM2 Controller initialize */
        ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
index 71ec4b7..db45331 100644 (file)
@@ -390,7 +390,7 @@ void mem_init(void)
 
        /* enable MPDDR clock */
        at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* DDRAM2 Controller initialize */
        ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
index de4291f..357b223 100644 (file)
@@ -386,7 +386,7 @@ void mem_init(void)
 
        /* enable MPDDR clock */
        at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* DDRAM2 Controller initialize */
        ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
index d74743f..3294203 100644 (file)
@@ -149,7 +149,7 @@ void mem_init(void)
        ddr2_conf(&ddr2);
 
        /* enable DDR2 clock */
-       writel(0x4, &pmc->scer);
+       writel(AT91_PMC_DDR, &pmc->scer);
 
        /* DDRAM2 Controller initialize */
        ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);