PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge

Logic and code for clearing PCI_EXP_LNKCTL_CLKREQ_EN bit is correct, but
comment describing it is misleading. PCI_EXP_LNKCTL_CLKREQ_EN bit should be
hardwired to zero but mvebu hw allows to change it.

Link: https://lore.kernel.org/r/20220104153529.31647-11-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>

diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 216da126a06de9fc1ff1567878e645f3e0ac5bbe..48098deb9b7bc6280b7dda2297c0e945c2a01fcd 100644 (file)
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -663,10 +663,9 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
 
        case PCI_EXP_LNKCTL:
                /*
-                * If we don't support CLKREQ, we must ensure that the
-                * CLKREQ enable bit always reads zero.  Since we haven't
-                * had this capability, and it's dependent on board wiring,
-                * disable it for the time being.
+                * PCIe requires that the Enable Clock Power Management bit
+                * is hard-wired to zero for downstream ports but HW allows
+                * to change it.
                 */
                new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;