imx8m: fix reading of DDR4 MR registers [again]

Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a
private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board
code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version
actually seems to work in practice.

However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c,
copied most of the rest of ddrphy_utils.c to
drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building
drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally
completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused
file)].

I assume this must have broken the imx8mm-cl-iot-gate board, at least
those that have not had their eeprom programmed with the proper
information. It certainly did break our out-of-tree board which always
reads back the ID register and uses that for a sanity check.

So apply the fix from 290ffe5788 once again.

Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>

diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index d964184..52a4aa6 100644 (file)
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -134,8 +134,14 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
                tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
        } while ((tmp & 0x8) == 0);
        tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
-       tmp = tmp & 0xff;
        reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+       while (tmp) { //try to find a significant byte in the word
+               if (tmp & 0xff) {
+                       tmp &= 0xff;
+                       break;
+               }
+               tmp >>= 8;
+       }
 
        return tmp;
 }