net: ethernet: stmicro: stmmac: dwmac-rk: Add rv1126 support

Rockchip RV1126 has GMAC 10/100/1000M ethernet controller
via RGMII and RMII interfaces are configured via M0 and M1 pinmux.

This patch adds rv1126 support by adding delay lines of M0 and M1
simultaneously.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220920140944.2535-2-anand@edgeble.ai
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 15dea1f..f7269d7 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1297,6 +1297,130 @@ static const struct rk_gmac_ops rv1108_ops = {
        .set_rmii_speed = rv1108_set_rmii_speed,
 };
 
+#define RV1126_GRF_GMAC_CON0           0X0070
+#define RV1126_GRF_GMAC_CON1           0X0074
+#define RV1126_GRF_GMAC_CON2           0X0078
+
+/* RV1126_GRF_GMAC_CON0 */
+#define RV1126_GMAC_PHY_INTF_SEL_RGMII \
+               (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RV1126_GMAC_PHY_INTF_SEL_RMII  \
+               (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RV1126_GMAC_FLOW_CTRL                  GRF_BIT(7)
+#define RV1126_GMAC_FLOW_CTRL_CLR              GRF_CLR_BIT(7)
+#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE                GRF_BIT(1)
+#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE       GRF_CLR_BIT(1)
+#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE                GRF_BIT(0)
+#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE       GRF_CLR_BIT(0)
+#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE                GRF_BIT(3)
+#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE       GRF_CLR_BIT(3)
+#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE                GRF_BIT(2)
+#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE       GRF_CLR_BIT(2)
+
+/* RV1126_GRF_GMAC_CON1 */
+#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val)      HIWORD_UPDATE(val, 0x7F, 8)
+#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val)      HIWORD_UPDATE(val, 0x7F, 0)
+/* RV1126_GRF_GMAC_CON2 */
+#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val)      HIWORD_UPDATE(val, 0x7F, 8)
+#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val)      HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
+                               int tx_delay, int rx_delay)
+{
+       struct device *dev = &bsp_priv->pdev->dev;
+
+       if (IS_ERR(bsp_priv->grf)) {
+               dev_err(dev, "Missing rockchip,grf property\n");
+               return;
+       }
+
+       regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
+                    RV1126_GMAC_PHY_INTF_SEL_RGMII |
+                    RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
+                    RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
+                    RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
+                    RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
+
+       regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
+                    RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
+                    RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
+
+       regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
+                    RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
+                    RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+       struct device *dev = &bsp_priv->pdev->dev;
+
+       if (IS_ERR(bsp_priv->grf)) {
+               dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+               return;
+       }
+
+       regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
+                    RV1126_GMAC_PHY_INTF_SEL_RMII);
+}
+
+static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+       struct device *dev = &bsp_priv->pdev->dev;
+       unsigned long rate;
+       int ret;
+
+       switch (speed) {
+       case 10:
+               rate = 2500000;
+               break;
+       case 100:
+               rate = 25000000;
+               break;
+       case 1000:
+               rate = 125000000;
+               break;
+       default:
+               dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
+               return;
+       }
+
+       ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
+       if (ret)
+               dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
+                       __func__, rate, ret);
+}
+
+static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+       struct device *dev = &bsp_priv->pdev->dev;
+       unsigned long rate;
+       int ret;
+
+       switch (speed) {
+       case 10:
+               rate = 2500000;
+               break;
+       case 100:
+               rate = 25000000;
+               break;
+       default:
+               dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
+               return;
+       }
+
+       ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
+       if (ret)
+               dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
+                       __func__, rate, ret);
+}
+
+static const struct rk_gmac_ops rv1126_ops = {
+       .set_to_rgmii = rv1126_set_to_rgmii,
+       .set_to_rmii = rv1126_set_to_rmii,
+       .set_rgmii_speed = rv1126_set_rgmii_speed,
+       .set_rmii_speed = rv1126_set_rmii_speed,
+};
+
 #define RK_GRF_MACPHY_CON0             0xb00
 #define RK_GRF_MACPHY_CON1             0xb04
 #define RK_GRF_MACPHY_CON2             0xb08
@@ -1836,6 +1960,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = {
        { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
        { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
        { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
+       { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
        { }
 };
 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);