-//===-- AMDGPUUnifyMetadata.cpp - Unify OpenCL metadata -------------------===//
+//===- AMDGPUUnifyMetadata.cpp - Unify OpenCL metadata --------------------===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/Constants.h"
-#include "llvm/IR/Function.h"
+#include "llvm/IR/Metadata.h"
#include "llvm/IR/Module.h"
#include "llvm/Pass.h"
#include <algorithm>
class AMDGPUUnifyMetadata : public ModulePass {
public:
static char ID;
- explicit AMDGPUUnifyMetadata() : ModulePass(ID) {};
+
+ explicit AMDGPUUnifyMetadata() : ModulePass(ID) {}
private:
- virtual bool runOnModule(Module &M);
+ bool runOnModule(Module &M) override;
/// \brief Unify version metadata.
/// \return true if changes are made.
-//===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ---------===//
+//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
+#include "AMDGPU.h"
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "MCTargetDesc/AMDGPUTargetStreamer.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/AMDGPUCodeObjectMetadata.h"
#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SMLoc.h"
AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)
: MCParsedAsmOperand(), Kind(Kind_), AsmParser(AsmParser_) {}
- typedef std::unique_ptr<AMDGPUOperand> Ptr;
+ using Ptr = std::unique_ptr<AMDGPUOperand>;
struct Modifiers {
bool Abs = false;
Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
};
- typedef std::map<AMDGPUOperand::ImmTy, unsigned> OptionalImmIndexMap;
+ using OptionalImmIndexMap = std::map<AMDGPUOperand::ImmTy, unsigned>;
AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
const MCInstrInfo &MII,
private:
struct OperandInfoTy {
int64_t Id;
- bool IsSymbolic;
- OperandInfoTy(int64_t Id_) : Id(Id_), IsSymbolic(false) { }
+ bool IsSymbolic = false;
+
+ OperandInfoTy(int64_t Id_) : Id(Id_) {}
};
bool parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId);
}
void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
-
if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
Inst.getNumOperands())) {
addLiteralImmOperand(Inst, Imm.Val,
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
- case AMDGPU::OPERAND_REG_INLINE_C_FP64: {
+ case AMDGPU::OPERAND_REG_INLINE_C_FP64:
if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
// unclear how we should encode them. This case should be checked earlier
// in predicate methods (isLiteralImm())
llvm_unreachable("fp literal in 64-bit integer instruction.");
- }
+
case AMDGPU::OPERAND_REG_IMM_INT32:
case AMDGPU::OPERAND_REG_IMM_FP32:
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
case AMDGPU::OPERAND_REG_IMM_INT32:
case AMDGPU::OPERAND_REG_IMM_FP32:
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
- case AMDGPU::OPERAND_REG_INLINE_C_FP32: {
+ case AMDGPU::OPERAND_REG_INLINE_C_FP32:
if (isInt<32>(Val) &&
AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val),
AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));
return;
- }
+
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
- case AMDGPU::OPERAND_REG_INLINE_C_FP64: {
+ case AMDGPU::OPERAND_REG_INLINE_C_FP64:
if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val));
return;
Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
return;
- }
+
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_IMM_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
- case AMDGPU::OPERAND_REG_INLINE_C_FP16: {
+ case AMDGPU::OPERAND_REG_INLINE_C_FP16:
if (isInt<16>(Val) &&
AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val),
AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val & 0xffff));
return;
- }
+
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
auto LiteralVal = static_cast<uint16_t>(Literal.getLoBits(16).getZExtValue());
if (AbsMod && getLexer().peekTok().is(AsmToken::Pipe) &&
(getLexer().getKind() == AsmToken::Integer ||
getLexer().getKind() == AsmToken::Real)) {
-
// This is a workaround for handling operands like these:
// |1.0|
// |-1|
SIInstrFlags::VOP1 | SIInstrFlags::VOP2 |
SIInstrFlags::VOP3 | SIInstrFlags::VOP3P |
SIInstrFlags::SDWA)) {
-
// Check special imm operands (used by madmk, etc)
if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) {
++ConstantBusUseCount;
}
bool AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) {
-
const unsigned Opcode = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opcode);
&& Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
}
-void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) {
-
+void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
+{
OptionalImmIndexMap OptionalIdx;
unsigned Opc = Inst.getOpcode();
if (getLexer().isNot(AsmToken::RBrac))
return MatchOperand_ParseFail;
Parser.Lex();
-
} else {
// sel:%d
Parser.Lex();
void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
uint64_t BasicInstType, bool skipVcc) {
using namespace llvm::AMDGPU::SDWA;
+
OptionalImmIndexMap OptionalIdx;
bool skippedVcc = false;
-//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
+//===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
//
// The LLVM Compiler Infrastructure
//
// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
-#include "AMDGPUDisassembler.h"
+#include "Disassembler/AMDGPUDisassembler.h"
#include "AMDGPU.h"
#include "AMDGPURegisterInfo.h"
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "Utils/AMDGPUBaseInfo.h"
-
+#include "llvm-c/Disassembler.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/Debug.h"
#include "llvm/Support/Endian.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/raw_ostream.h"
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <iterator>
+#include <tuple>
+#include <vector>
using namespace llvm;
#define DEBUG_TYPE "amdgpu-disassembler"
-typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
-
+using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
inline static MCDisassembler::DecodeStatus
addOperand(MCInst &Inst, const MCOperand& Opnd) {
DECODE_OPERAND_REG(SReg_256)
DECODE_OPERAND_REG(SReg_512)
-
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
unsigned Imm,
uint64_t Addr,
return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
}
-
MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
// For now all literal constants are supposed to be unsigned integer
// ToDo: deal with signed/unsigned 64-bit integer constants
MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
using namespace AMDGPU::EncValues;
+
assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
(static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
using namespace AMDGPU;
+
assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
switch (Width) {
default: // fall
unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
using namespace AMDGPU;
+
assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
switch (Width) {
default: // fall
unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
using namespace AMDGPU;
+
assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
switch (Width) {
default: // fall
MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
using namespace AMDGPU::EncValues;
+
assert(Val < 512); // enum9
if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
using namespace AMDGPU;
+
switch (Val) {
case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
using namespace AMDGPU;
+
switch (Val) {
case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
case 106: return createRegOperand(VCC);
return decodeSDWASrc(OPW32, Val);
}
-
MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
using namespace AMDGPU::SDWA;
raw_ostream &/*cStream*/, int64_t Value,
uint64_t /*Address*/, bool IsBranch,
uint64_t /*Offset*/, uint64_t /*InstSize*/) {
- typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy;
- typedef std::vector<SymbolInfoTy> SectionSymbolsTy;
+ using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
+ using SectionSymbolsTy = std::vector<SymbolInfoTy>;
if (!IsBranch) {
return false;
-//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
+//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
- DecodeStatus tryDecodeInst(const uint8_t* Table,
- MCInst &MI,
- uint64_t Inst,
- uint64_t Address) const;
+ DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
+ uint64_t Address) const;
DecodeStatus convertSDWAInst(MCInst &MI) const;
-//===--------------------- GCNIterativeScheduler.cpp - --------------------===//
+//===- GCNIterativeScheduler.cpp ------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-/// \file
-//
-//===----------------------------------------------------------------------===//
#include "GCNIterativeScheduler.h"
+#include "AMDGPUSubtarget.h"
+#include "GCNRegPressure.h"
#include "GCNSchedStrategy.h"
-#include "SIMachineFunctionInfo.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include <algorithm>
+#include <cassert>
+#include <iterator>
+#include <limits>
+#include <memory>
+#include <type_traits>
+#include <vector>
using namespace llvm;
#define DEBUG_TYPE "machine-scheduler"
namespace llvm {
- std::vector<const SUnit*> makeMinRegSchedule(ArrayRef<const SUnit*> TopRoots,
- const ScheduleDAG &DAG);
-}
+
+std::vector<const SUnit *> makeMinRegSchedule(ArrayRef<const SUnit *> TopRoots,
+ const ScheduleDAG &DAG);
+
+} // end namespace llvm
// shim accessors for different order containers
static inline MachineInstr *getMachineInstr(MachineInstr *MI) {
OS << "RP after: ";
After.print(OS, &ST);
}
-
#endif
// DAG builder helper
class GCNIterativeScheduler::BuildDAG {
GCNIterativeScheduler &Sch;
- SmallVector<SUnit*, 8> TopRoots;
+ SmallVector<SUnit *, 8> TopRoots;
+
public:
BuildDAG(const Region &R, GCNIterativeScheduler &_Sch)
: Sch(_Sch) {
/*TrackLaneMask*/true);
Sch.Topo.InitDAGTopologicalSorting();
- SmallVector<SUnit*, 8> BotRoots;
+ SmallVector<SUnit *, 8> BotRoots;
Sch.findRootsAndBiasEdges(TopRoots, BotRoots);
}
+
~BuildDAG() {
Sch.BaseClass::exitRegion();
Sch.BaseClass::finishBlock();
}
- ArrayRef<const SUnit*> getTopRoots() const {
+
+ ArrayRef<const SUnit *> getTopRoots() const {
return TopRoots;
}
};
Region &Rgn;
std::unique_ptr<MachineSchedStrategy> SaveSchedImpl;
GCNRegPressure SaveMaxRP;
+
public:
OverrideLegacyStrategy(Region &R,
MachineSchedStrategy &OverrideStrategy,
Sch.BaseClass::startBlock(BB);
Sch.BaseClass::enterRegion(BB, R.Begin, R.End, R.NumRegionInstrs);
}
+
~OverrideLegacyStrategy() {
Sch.BaseClass::exitRegion();
Sch.BaseClass::finishBlock();
Sch.SchedImpl.release();
Sch.SchedImpl = std::move(SaveSchedImpl);
}
+
void schedule() {
assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End);
DEBUG(dbgs() << "\nScheduling ";
Rgn.Begin = Sch.RegionBegin;
Rgn.MaxPressure.clear();
}
+
void restoreOrder() {
assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End);
// DAG SUnits are stored using original region's order
};
namespace {
+
// just a stub to make base class happy
class SchedStrategyStub : public MachineSchedStrategy {
public:
void releaseTopNode(SUnit *SU) override {}
void releaseBottomNode(SUnit *SU) override {}
};
-} // namespace
+
+} // end anonymous namespace
GCNIterativeScheduler::GCNIterativeScheduler(MachineSchedContext *C,
StrategyKind S)
-//===--------- GCNIterativeScheduler.h - GCN Scheduler -*- C++ -*----------===//
+//===- GCNIterativeScheduler.h - GCN Scheduler ------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-/// \file
-//
-//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H
#define LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H
#include "GCNRegPressure.h"
-
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineScheduler.h"
+#include "llvm/Support/Allocator.h"
+#include <limits>
+#include <memory>
+#include <vector>
namespace llvm {
+class MachineInstr;
+class SUnit;
+class raw_ostream;
+
class GCNIterativeScheduler : public ScheduleDAGMILive {
- typedef ScheduleDAGMILive BaseClass;
+ using BaseClass = ScheduleDAGMILive;
+
public:
enum StrategyKind {
SCHEDULE_MINREGONLY,
void finalizeSchedule() override;
protected:
-
- typedef ArrayRef<const SUnit*> ScheduleRef;
+ using ScheduleRef = ArrayRef<const SUnit *>;
struct TentativeSchedule {
- std::vector<MachineInstr*> Schedule;
+ std::vector<MachineInstr *> Schedule;
GCNRegPressure MaxPressure;
};
const GCNRegPressure &After) const;
};
-} // End namespace llvm
+} // end namespace llvm
#endif // LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H
-//===------------------------- GCNRegPressure.cpp - -----------------------===//
+//===- GCNRegPressure.cpp -------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-/// \file
-//
-//===----------------------------------------------------------------------===//
#include "GCNRegPressure.h"
+#include "AMDGPUSubtarget.h"
+#include "SIRegisterInfo.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include <algorithm>
+#include <cassert>
using namespace llvm;
}
return true;
}
-
#endif
///////////////////////////////////////////////////////////////////////////////
}
#endif
-
static LaneBitmask getDefRegMask(const MachineOperand &MO,
const MachineRegisterInfo &MRI) {
assert(MO.isDef() && MO.isReg() &&
-//===---------------------- GCNRegPressure.h -*- C++ -*--------------------===//
+//===- GCNRegPressure.h -----------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-/// \file
-//
-//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
#define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
#include "AMDGPUSubtarget.h"
-
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Support/Debug.h"
+#include <algorithm>
#include <limits>
namespace llvm {
+class MachineRegisterInfo;
+class raw_ostream;
+
struct GCNRegPressure {
enum RegKind {
SGPR32,
return !(*this == O);
}
- void print(raw_ostream &OS, const SISubtarget *ST=nullptr) const;
+ void print(raw_ostream &OS, const SISubtarget *ST = nullptr) const;
void dump() const { print(dbgs()); }
private:
class GCNRPTracker {
public:
- typedef DenseMap<unsigned, LaneBitmask> LiveRegSet;
+ using LiveRegSet = DenseMap<unsigned, LaneBitmask>;
protected:
const LiveIntervals &LIS;
GCNRegPressure CurPressure, MaxPressure;
const MachineInstr *LastTrackedMI = nullptr;
mutable const MachineRegisterInfo *MRI = nullptr;
+
GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
+
public:
// live regs for the current state
const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
MaxPressure.clear();
return Res;
}
+
decltype(LiveRegs) moveLiveRegs() {
return std::move(LiveRegs);
}
+
static void printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
const MachineRegisterInfo &MRI);
};
class GCNUpwardRPTracker : public GCNRPTracker {
public:
GCNUpwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {}
+
// reset tracker to the point just below MI
// filling live regs upon this point using LIS
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
const LiveIntervals &LIS,
const MachineRegisterInfo &MRI);
-} // End namespace llvm
+} // end namespace llvm
#endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
-//===-- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst----------===//
+//===- R600ControlFlowFinalizer.cpp - Finalize Control Flow Inst ----------===//
//
// The LLVM Compiler Infrastructure
//
//
/// \file
/// This pass compute turns all control flow pseudo instructions into native one
-/// computing their address on the fly ; it also sets STACK_SIZE info.
+/// computing their address on the fly; it also sets STACK_SIZE info.
+//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/Function.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
-#include <new>
#include <set>
#include <utility>
#include <vector>
namespace {
struct CFStack {
-
enum StackItem {
ENTRY = 0,
SUB_ENTRY = 1,
class R600ControlFlowFinalizer : public MachineFunctionPass {
private:
- typedef std::pair<MachineInstr *, std::vector<MachineInstr *>> ClauseFile;
+ using ClauseFile = std::pair<MachineInstr *, std::vector<MachineInstr *>>;
enum ControlFlowInstruction {
CF_TC,
-//===-- R600ExpandSpecialInstrs.cpp - Expand special instructions ---------===//
+//===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
//
// The LLVM Compiler Infrastructure
//
#include "AMDGPUSubtarget.h"
#include "R600Defines.h"
#include "R600InstrInfo.h"
-#include "R600MachineFunctionInfo.h"
#include "R600RegisterInfo.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/Pass.h"
+#include <cassert>
+#include <cstdint>
+#include <iterator>
using namespace llvm;
class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
private:
- const R600InstrInfo *TII;
+ const R600InstrInfo *TII = nullptr;
void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
unsigned Op);
public:
static char ID;
- R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID),
- TII(nullptr) { }
+ R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
}
};
-} // End anonymous namespace
+} // end anonymous namespace
INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
"R600 Expand Special Instrs", false, false)
continue;
}
case AMDGPU::DOT_4: {
-
const R600RegisterInfo &TRI = TII->getRegisterInfo();
unsigned DstReg = MI.getOperand(0).getReg();
-//===--------------------- R600MergeVectorRegisters.cpp -------------------===//
+//===- R600MergeVectorRegisters.cpp ---------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
-#include "llvm/PassAnalysisSupport.h"
+#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
class R600VectorRegMerger : public MachineFunctionPass {
private:
+ using InstructionSetMap = DenseMap<unsigned, std::vector<MachineInstr *>>;
+
MachineRegisterInfo *MRI;
- const R600InstrInfo *TII;
+ const R600InstrInfo *TII = nullptr;
+ DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq;
+ InstructionSetMap PreviousRegSeqByReg;
+ InstructionSetMap PreviousRegSeqByUndefCount;
bool canSwizzle(const MachineInstr &MI) const;
bool areAllUsesSwizzeable(unsigned Reg) const;
void RemoveMI(MachineInstr *);
void trackRSI(const RegSeqInfo &RSI);
- typedef DenseMap<unsigned, std::vector<MachineInstr *>> InstructionSetMap;
- DenseMap<MachineInstr *, RegSeqInfo> PreviousRegSeq;
- InstructionSetMap PreviousRegSeqByReg;
- InstructionSetMap PreviousRegSeqByUndefCount;
-
public:
static char ID;
- R600VectorRegMerger() : MachineFunctionPass(ID),
- TII(nullptr) { }
+ R600VectorRegMerger() : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
bool runOnMachineFunction(MachineFunction &Fn) override;
};
-} // end anonymous namespace.
+} // end anonymous namespace
INITIALIZE_PASS_BEGIN(R600VectorRegMerger, DEBUG_TYPE,
"R600 Vector Reg Merger", false, false)
-//===--- SIMemoryLegalizer.cpp ----------------------------------*- C++ -*-===//
+//===- SIMemoryLegalizer.cpp ----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
/// \brief Memory legalizer - implements memory model. More information can be
/// found here:
/// http://llvm.org/docs/AMDGPUUsage.html#memory-model
-///
//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPUMachineModuleInfo.h"
#include "AMDGPUSubtarget.h"
+#include "SIDefines.h"
+#include "SIInstrInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
+#include "llvm/ADT/None.h"
+#include "llvm/ADT/Optional.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DiagnosticInfo.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/AtomicOrdering.h"
+#include <cassert>
+#include <list>
using namespace llvm;
using namespace llvm::AMDGPU;
AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent;
AtomicOrdering FailureOrdering = AtomicOrdering::SequentiallyConsistent;
- AtomicInfo() {}
+ AtomicInfo() = default;
AtomicInfo(SyncScope::ID SSID,
AtomicOrdering Ordering,
/// \brief LLVM context.
LLVMContext *CTX = nullptr;
+
/// \brief Machine module info.
const AMDGPUMachineModuleInfo *MMI = nullptr;
+
/// \brief Instruction info.
const SIInstrInfo *TII = nullptr;
/// \brief Immediate for "vmcnt(0)".
unsigned Vmcnt0Immediate = 0;
+
/// \brief Opcode for cache invalidation instruction (L1).
unsigned Wbinvl1Opcode = 0;
public:
static char ID;
- SIMemoryLegalizer()
- : MachineFunctionPass(ID) {}
+ SIMemoryLegalizer() : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
-//===--------------------AMDKernelCodeTUtils.cpp --------------------------===//
+//===- AMDKernelCodeTUtils.cpp --------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-//===----------------------------------------------------------------------===//
-//
/// \file - utility functions to parse/print amd_kernel_code_t structure
//
//===----------------------------------------------------------------------===//
#include "AMDKernelCodeTUtils.h"
#include "SIDefines.h"
-#include <llvm/MC/MCParser/MCAsmLexer.h>
-#include <llvm/MC/MCParser/MCAsmParser.h>
-#include <llvm/Support/raw_ostream.h>
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/MC/MCParser/MCAsmLexer.h"
+#include "llvm/MC/MCParser/MCAsmParser.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <cstdint>
+#include <utility>
using namespace llvm;
return get_amd_kernel_code_t_FldNames()[index + 1];
}
-
// Field printing
static raw_ostream &printName(raw_ostream &OS, StringRef Name) {
printName(OS, Name) << (int)((c.*ptr >> shift) & Mask);
}
-typedef void(*PrintFx)(StringRef,
- const amd_kernel_code_t &,
- raw_ostream &);
+using PrintFx = void(*)(StringRef, const amd_kernel_code_t &, raw_ostream &);
static ArrayRef<PrintFx> getPrinterTable() {
static const PrintFx Table[] = {
}
}
-
// Field parsing
static bool expectAbsExpression(MCAsmParser &MCParser, int64_t &Value, raw_ostream& Err) {
return true;
}
-typedef bool(*ParseFx)(amd_kernel_code_t &,
- MCAsmParser &MCParser,
- raw_ostream &Err);
+using ParseFx = bool(*)(amd_kernel_code_t &, MCAsmParser &MCParser,
+ raw_ostream &Err);
static ArrayRef<ParseFx> getParserTable() {
static const ParseFx Table[] = {
-//===- AMDGPUKernelCodeTUtils.h - helpers for amd_kernel_code_t *- C++ -*-===//
+//===- AMDGPUKernelCodeTUtils.h - helpers for amd_kernel_code_t -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
/// \file AMDKernelCodeTUtils.h
+//
//===----------------------------------------------------------------------===//
-#ifndef AMDKERNELCODETUTILS_H
-#define AMDKERNELCODETUTILS_H
+#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H
+#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H
#include "AMDKernelCodeT.h"
namespace llvm {
-class MCAsmLexer;
class MCAsmParser;
class raw_ostream;
class StringRef;
-void printAmdKernelCodeField(const amd_kernel_code_t &C,
- int FldIndex,
- raw_ostream &OS);
+void printAmdKernelCodeField(const amd_kernel_code_t &C, int FldIndex,
+ raw_ostream &OS);
-void dumpAmdKernelCode(const amd_kernel_code_t *C,
- raw_ostream &OS,
- const char *tab);
+void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS,
+ const char *tab);
-bool parseAmdKernelCodeField(StringRef ID,
- MCAsmParser &Parser,
- amd_kernel_code_t &C,
- raw_ostream &Err);
+bool parseAmdKernelCodeField(StringRef ID, MCAsmParser &Parser,
+ amd_kernel_code_t &C, raw_ostream &Err);
-}
+} // end namespace llvm
-#endif // AMDKERNELCODETUTILS_H
+#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H