ASoC: Intel: avs: APL-based platforms support
authorCezary Rojewski <cezary.rojewski@intel.com>
Mon, 16 May 2022 10:11:16 +0000 (12:11 +0200)
committerMark Brown <broonie@kernel.org>
Tue, 17 May 2022 10:58:08 +0000 (11:58 +0100)
Define handlers specific to cAVS 1.5+ platforms, that is, APL and
similar platforms. These differ from SKL-alike ones in terms of AudioDSP
firmware generation and thus the '+' suffix. Introduciton of IMR,
removal of CLDMA, D0IX support and monolithic-ation of library/module
code are most impactful but are not the only changes brought with this
newer generation. Some generic and 1.5 operations are being re-used to
reduce code size.

Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20220516101116.190192-16-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/intel/avs/Makefile
sound/soc/intel/avs/apl.c [new file with mode: 0644]
sound/soc/intel/avs/avs.h
sound/soc/intel/avs/core.c
sound/soc/intel/avs/loader.c
sound/soc/intel/avs/messages.h
sound/soc/intel/avs/registers.h

index 7d09385bc9707b2df7d012259d9ee85af6f47ed1..b6b93ae80304b2c4df596b29950f90b444a4cfb6 100644 (file)
@@ -3,7 +3,7 @@
 snd-soc-avs-objs := dsp.o ipc.o messages.o utils.o core.o loader.o \
                    topology.o path.o pcm.o board_selection.o
 snd-soc-avs-objs += cldma.o
-snd-soc-avs-objs += skl.o
+snd-soc-avs-objs += skl.o apl.o
 
 snd-soc-avs-objs += trace.o
 # tell define_trace.h where to find the trace header
diff --git a/sound/soc/intel/avs/apl.c b/sound/soc/intel/avs/apl.c
new file mode 100644 (file)
index 0000000..b8e2b23
--- /dev/null
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
+//
+// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
+//          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
+//
+
+#include <linux/devcoredump.h>
+#include <linux/slab.h>
+#include "avs.h"
+#include "messages.h"
+#include "path.h"
+#include "topology.h"
+
+static int apl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
+                          u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
+{
+       struct apl_log_state_info *info;
+       u32 size, num_cores = adev->hw_cfg.dsp_cores;
+       int ret, i;
+
+       if (fls_long(resource_mask) > num_cores)
+               return -EINVAL;
+       size = struct_size(info, logs_core, num_cores);
+       info = kzalloc(size, GFP_KERNEL);
+       if (!info)
+               return -ENOMEM;
+
+       info->aging_timer_period = aging_period;
+       info->fifo_full_timer_period = fifo_full_period;
+       info->core_mask = resource_mask;
+       if (enable)
+               for_each_set_bit(i, &resource_mask, num_cores) {
+                       info->logs_core[i].enable = enable;
+                       info->logs_core[i].min_priority = *priorities++;
+               }
+       else
+               for_each_set_bit(i, &resource_mask, num_cores)
+                       info->logs_core[i].enable = enable;
+
+       ret = avs_ipc_set_enable_logs(adev, (u8 *)info, size);
+       kfree(info);
+       if (ret)
+               return AVS_IPC_RET(ret);
+
+       return 0;
+}
+
+static int apl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
+{
+       struct apl_log_buffer_layout layout;
+       unsigned long flags;
+       void __iomem *addr, *buf;
+
+       addr = avs_log_buffer_addr(adev, msg->log.core);
+       if (!addr)
+               return -ENXIO;
+
+       memcpy_fromio(&layout, addr, sizeof(layout));
+
+       spin_lock_irqsave(&adev->dbg.trace_lock, flags);
+       if (!kfifo_initialized(&adev->dbg.trace_fifo))
+               /* consume the logs regardless of consumer presence */
+               goto update_read_ptr;
+
+       buf = apl_log_payload_addr(addr);
+
+       if (layout.read_ptr > layout.write_ptr) {
+               __kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
+                                     apl_log_payload_size(adev) - layout.read_ptr,
+                                     &adev->dbg.fifo_lock);
+               layout.read_ptr = 0;
+       }
+       __kfifo_fromio_locked(&adev->dbg.trace_fifo, buf + layout.read_ptr,
+                             layout.write_ptr - layout.read_ptr, &adev->dbg.fifo_lock);
+
+       wake_up(&adev->dbg.trace_waitq);
+
+update_read_ptr:
+       spin_unlock_irqrestore(&adev->dbg.trace_lock, flags);
+       writel(layout.write_ptr, addr);
+       return 0;
+}
+
+static int apl_wait_log_entry(struct avs_dev *adev, u32 core, struct apl_log_buffer_layout *layout)
+{
+       unsigned long timeout;
+       void __iomem *addr;
+
+       addr = avs_log_buffer_addr(adev, core);
+       if (!addr)
+               return -ENXIO;
+
+       timeout = jiffies + msecs_to_jiffies(10);
+
+       do {
+               memcpy_fromio(layout, addr, sizeof(*layout));
+               if (layout->read_ptr != layout->write_ptr)
+                       return 0;
+               usleep_range(500, 1000);
+       } while (!time_after(jiffies, timeout));
+
+       return -ETIMEDOUT;
+}
+
+/* reads log header and tests its type */
+#define apl_is_entry_stackdump(addr) ((readl(addr) >> 30) & 0x1)
+
+static int apl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
+{
+       struct apl_log_buffer_layout layout;
+       void __iomem *addr, *buf;
+       size_t dump_size;
+       u16 offset = 0;
+       u8 *dump, *pos;
+
+       dump_size = AVS_FW_REGS_SIZE + msg->ext.coredump.stack_dump_size;
+       dump = vzalloc(dump_size);
+       if (!dump)
+               return -ENOMEM;
+
+       memcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
+
+       if (!msg->ext.coredump.stack_dump_size)
+               goto exit;
+
+       /* Dump the registers even if an external error prevents gathering the stack. */
+       addr = avs_log_buffer_addr(adev, msg->ext.coredump.core_id);
+       if (!addr)
+               goto exit;
+
+       buf = apl_log_payload_addr(addr);
+       memcpy_fromio(&layout, addr, sizeof(layout));
+       if (!apl_is_entry_stackdump(buf + layout.read_ptr)) {
+               /*
+                * DSP awaits the remaining logs to be
+                * gathered before dumping stack
+                */
+               msg->log.core = msg->ext.coredump.core_id;
+               avs_dsp_op(adev, log_buffer_status, msg);
+       }
+
+       pos = dump + AVS_FW_REGS_SIZE;
+       /* gather the stack */
+       do {
+               u32 count;
+
+               if (apl_wait_log_entry(adev, msg->ext.coredump.core_id, &layout))
+                       break;
+
+               if (layout.read_ptr > layout.write_ptr) {
+                       count = apl_log_payload_size(adev) - layout.read_ptr;
+                       memcpy_fromio(pos + offset, buf + layout.read_ptr, count);
+                       layout.read_ptr = 0;
+                       offset += count;
+               }
+               count = layout.write_ptr - layout.read_ptr;
+               memcpy_fromio(pos + offset, buf + layout.read_ptr, count);
+               offset += count;
+
+               /* update read pointer */
+               writel(layout.write_ptr, addr);
+       } while (offset < msg->ext.coredump.stack_dump_size);
+
+exit:
+       dev_coredumpv(adev->dev, dump, dump_size, GFP_KERNEL);
+
+       return 0;
+}
+
+static bool apl_lp_streaming(struct avs_dev *adev)
+{
+       struct avs_path *path;
+
+       /* Any gateway without buffer allocated in LP area disqualifies D0IX. */
+       list_for_each_entry(path, &adev->path_list, node) {
+               struct avs_path_pipeline *ppl;
+
+               list_for_each_entry(ppl, &path->ppl_list, node) {
+                       struct avs_path_module *mod;
+
+                       list_for_each_entry(mod, &ppl->mod_list, node) {
+                               struct avs_tplg_modcfg_ext *cfg;
+
+                               cfg = mod->template->cfg_ext;
+
+                               /* only copiers have gateway attributes */
+                               if (!guid_equal(&cfg->type, &AVS_COPIER_MOD_UUID))
+                                       continue;
+                               /* non-gateway copiers do not prevent PG */
+                               if (cfg->copier.dma_type == INVALID_OBJECT_ID)
+                                       continue;
+
+                               if (!mod->gtw_attrs.lp_buffer_alloc)
+                                       return false;
+                       }
+               }
+       }
+
+       return true;
+}
+
+static bool apl_d0ix_toggle(struct avs_dev *adev, struct avs_ipc_msg *tx, bool wake)
+{
+       /* wake in all cases */
+       if (wake)
+               return true;
+
+       /*
+        * If no pipelines are running, allow for d0ix schedule.
+        * If all gateways have lp=1, allow for d0ix schedule.
+        * If any gateway with lp=0 is allocated, abort scheduling d0ix.
+        *
+        * Note: for cAVS 1.5+ and 1.8, D0IX is LP-firmware transition,
+        * not the power-gating mechanism known from cAVS 2.0.
+        */
+       return apl_lp_streaming(adev);
+}
+
+static int apl_set_d0ix(struct avs_dev *adev, bool enable)
+{
+       bool streaming = false;
+       int ret;
+
+       if (enable)
+               /* Either idle or all gateways with lp=1. */
+               streaming = !list_empty(&adev->path_list);
+
+       ret = avs_ipc_set_d0ix(adev, enable, streaming);
+       return AVS_IPC_RET(ret);
+}
+
+const struct avs_dsp_ops apl_dsp_ops = {
+       .power = avs_dsp_core_power,
+       .reset = avs_dsp_core_reset,
+       .stall = avs_dsp_core_stall,
+       .irq_handler = avs_dsp_irq_handler,
+       .irq_thread = avs_dsp_irq_thread,
+       .int_control = avs_dsp_interrupt_control,
+       .load_basefw = avs_hda_load_basefw,
+       .load_lib = avs_hda_load_library,
+       .transfer_mods = avs_hda_transfer_modules,
+       .enable_logs = apl_enable_logs,
+       .log_buffer_offset = skl_log_buffer_offset,
+       .log_buffer_status = apl_log_buffer_status,
+       .coredump = apl_coredump,
+       .d0ix_toggle = apl_d0ix_toggle,
+       .set_d0ix = apl_set_d0ix,
+};
index 237e4422dcaddb501c4ab52e62b6451a4e73ab2a..92e37722d280b5820ff48b7206943c28f9eb068b 100644 (file)
@@ -57,6 +57,7 @@ struct avs_dsp_ops {
        ((adev)->spec->dsp_ops->op(adev, ## __VA_ARGS__))
 
 extern const struct avs_dsp_ops skl_dsp_ops;
+extern const struct avs_dsp_ops apl_dsp_ops;
 
 #define AVS_PLATATTR_CLDMA             BIT_ULL(0)
 #define AVS_PLATATTR_IMR               BIT_ULL(1)
@@ -333,4 +334,16 @@ unsigned int __kfifo_fromio_locked(struct kfifo *fifo, const void __iomem *src,
                         (avs_sram_addr(adev, AVS_DEBUG_WINDOW) + __offset); \
 })
 
+struct apl_log_buffer_layout {
+       u32 read_ptr;
+       u32 write_ptr;
+       u8 buffer[];
+} __packed;
+
+#define apl_log_payload_size(adev) \
+       (avs_log_buffer_size(adev) - sizeof(struct apl_log_buffer_layout))
+
+#define apl_log_payload_addr(addr) \
+       (addr + sizeof(struct apl_log_buffer_layout))
+
 #endif /* __SOUND_SOC_INTEL_AVS_H */
index 7e78a9a9d16658e099eb00c66a77ad28b46dad71..3a0997c3af2b9aab472305422bbdb601ccae8201 100644 (file)
@@ -650,9 +650,27 @@ static const struct avs_spec skl_desc = {
        .rom_status = SKL_ADSP_SRAM_BASE_OFFSET,
 };
 
+static const struct avs_spec apl_desc = {
+       .name = "apl",
+       .min_fw_version = {
+               .major = 9,
+               .minor = 22,
+               .hotfix = 1,
+               .build = 4323,
+       },
+       .dsp_ops = &apl_dsp_ops,
+       .core_init_mask = 3,
+       .attributes = AVS_PLATATTR_IMR,
+       .sram_base_offset = APL_ADSP_SRAM_BASE_OFFSET,
+       .sram_window_size = APL_ADSP_SRAM_WINDOW_SIZE,
+       .rom_status = APL_ADSP_SRAM_BASE_OFFSET,
+};
+
 static const struct pci_device_id avs_ids[] = {
        { PCI_VDEVICE(INTEL, 0x9d70), (unsigned long)&skl_desc }, /* SKL */
        { PCI_VDEVICE(INTEL, 0x9d71), (unsigned long)&skl_desc }, /* KBL */
+       { PCI_VDEVICE(INTEL, 0x5a98), (unsigned long)&apl_desc }, /* APL */
+       { PCI_VDEVICE(INTEL, 0x3198), (unsigned long)&apl_desc }, /* GML */
        { 0 }
 };
 MODULE_DEVICE_TABLE(pci, avs_ids);
index 8aa658c5232513406d3f24be52eec5afbcb0c0af..542fd44aa501e5a65469f1926054c16d474d2914 100644 (file)
@@ -37,6 +37,8 @@
 #define AVS_EXT_MANIFEST_MAGIC         0x31454124
 #define SKL_MANIFEST_MAGIC             0x00000006
 #define SKL_ADSPFW_OFFSET              0x284
+#define APL_MANIFEST_MAGIC             0x44504324
+#define APL_ADSPFW_OFFSET              0x2000
 
 /* Occasionally, engineering (release candidate) firmware is provided for testing. */
 static bool debug_ignore_fw_version;
@@ -87,6 +89,8 @@ static int avs_fw_manifest_offset(struct firmware *fw)
        switch (magic) {
        case SKL_MANIFEST_MAGIC:
                return SKL_ADSPFW_OFFSET;
+       case APL_MANIFEST_MAGIC:
+               return APL_ADSPFW_OFFSET;
        default:
                return -EINVAL;
        }
index 981ec024b1527250cd87ae2c3c418c292a077286..c0f90dba9af89fde9e2846c2ce05d7ad354518f6 100644 (file)
@@ -365,6 +365,13 @@ struct skl_log_state_info {
        struct skl_log_state logs_core[];
 } __packed;
 
+struct apl_log_state_info {
+       u32 aging_timer_period;
+       u32 fifo_full_timer_period;
+       u32 core_mask;
+       struct skl_log_state logs_core[];
+} __packed;
+
 int avs_ipc_set_enable_logs(struct avs_dev *adev, u8 *log_info, size_t size);
 
 struct avs_fw_version {
index 68f06aa4e10fb357b9dcb63afc7d8b935c752a38..95be86148cf3a25db7c0ab24d339599fa559ba9e 100644 (file)
@@ -51,6 +51,8 @@
 /* Intel HD Audio SRAM windows base addresses */
 #define SKL_ADSP_SRAM_BASE_OFFSET      0x8000
 #define SKL_ADSP_SRAM_WINDOW_SIZE      0x2000
+#define APL_ADSP_SRAM_BASE_OFFSET      0x80000
+#define APL_ADSP_SRAM_WINDOW_SIZE      0x20000
 
 /* Constants used when accessing SRAM, space shared with firmware */
 #define AVS_FW_REG_BASE(adev)          ((adev)->spec->sram_base_offset)