83xx/85xx: further localbus cleanups

Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names
from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index a129dca..4529f02 100644 (file)
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -44,7 +44,11 @@
 #define BR_MSEL_SHIFT                  5
 #define BR_MS_GPCM                     0x00000000      /* GPCM */
 #define BR_MS_FCM                      0x00000020      /* FCM */
+#ifdef CONFIG_MPC83xx
 #define BR_MS_SDRAM                    0x00000060      /* SDRAM */
+#elif defined(CONFIG_MPC85xx)
+#define BR_MS_SDRAM                    0x00000000      /* SDRAM */
+#endif
 #define BR_MS_UPMA                     0x00000080      /* UPMA */
 #define BR_MS_UPMB                     0x000000A0      /* UPMB */
 #define BR_MS_UPMC                     0x000000C0      /* UPMC */
@@ -80,8 +84,8 @@
 #define OR_GPCM_CSNT_SHIFT             11
 #define OR_GPCM_ACS                    0x00000600
 #define OR_GPCM_ACS_SHIFT              9
-#define OR_GPCM_ACS_0b10               0x00000400
-#define OR_GPCM_ACS_0b11               0x00000600
+#define OR_GPCM_ACS_DIV2               0x00000600
+#define OR_GPCM_ACS_DIV4               0x00000400
 #define OR_GPCM_XACS                   0x00000100
 #define OR_GPCM_XACS_SHIFT             8
 #define OR_GPCM_SCY                    0x000000F0
@@ -110,6 +114,10 @@
 #define OR_GPCM_EAD                    0x00000001
 #define OR_GPCM_EAD_SHIFT              0
 
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s)  ((~((s) - 1)) & 0xffff8000)     /* must be pow of 2 */
+#define MEG_TO_AM(m)   P2SZ_TO_AM((m) << 20)
+
 #define OR_FCM_AM                      0xFFFF8000
 #define OR_FCM_AM_SHIFT                                15
 #define OR_FCM_BCTLD                   0x00001000
@@ -153,6 +161,11 @@
 #define OR_UPM_EAD                     0x00000001
 #define OR_UPM_EAD_SHIFT               0
 
+#define MxMR_OP_NORM                   0x00000000 /* Normal Operation */
+#define MxMR_DSx_2_CYCL                0x00400000 /* 2 cycle Disable Period */
+#define MxMR_OP_WARR                   0x10000000 /* Write to Array */
+#define MxMR_BSEL                      0x80000000 /* Bus Select */
+
 #define OR_SDRAM_AM                    0xFFFF8000
 #define OR_SDRAM_AM_SHIFT              15
 #define OR_SDRAM_XAM                   0x00006000

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 7a5d0aa..095f665 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -203,7 +203,7 @@
 #define CFG_OR0_PRELIM         ( (~(CFG_FLASH_SIZE - 1) << 20) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_0b11 \
+                               | OR_GPCM_ACS_DIV2 \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_15 \
                                | OR_GPCM_TRLX \

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index bd77540..37e3ca4 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -157,7 +157,7 @@
                                (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
                                BR_V)                   /* valid */
 #define CFG_OR0_PRELIM         ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
                                OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM   CFG_FLASH_BASE  /* window base at flash base */
 #define CFG_LBLAWAR0_PRELIM    0x80000018      /* 32 MB window size */

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 38410a1..82d0686 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #define CFG_BR0_PRELIM         (CFG_FLASH_BASE | BR_PS_16 | BR_V)
 #define CFG_OR0_PRELIM         ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
                                OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM   CFG_FLASH_BASE
 #define CFG_LBLAWAR0_PRELIM    (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
@@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #define CFG_LED_BASE           0xF9000000
 #define CFG_BR2_PRELIM         (CFG_LED_BASE | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM         (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+#define CFG_OR2_PRELIM         (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
                                OR_GPCM_EHTR | OR_GPCM_EAD)
 

diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index fcfbe6f..b4bff9a 100644 (file)
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -203,7 +203,7 @@
                        (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
                        BR_V)   /* valid */
 #define CFG_OR0_PRELIM         ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
                                OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 
 #define CFG_MAX_FLASH_BANKS    1 /* number of banks */

diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index adedcb9..ca8d53c 100644 (file)
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -195,7 +195,7 @@
                        (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
                        BR_V)   /* valid */
 #define CFG_OR0_PRELIM         ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
                                OR_GPCM_XACS | OR_GPCM_SCY_15 | \
                                OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 4e159a0..0dd0279 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -239,7 +239,7 @@
 #define CFG_OR0_PRELIM         ( (~(CFG_FLASH_SIZE - 1) << 20) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_0b11 \
+                               | OR_GPCM_ACS_DIV2 \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_15 \
                                | OR_GPCM_TRLX \

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 89fc465..0d2ca72 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks;
                                        BR_MS_GPCM | BR_PS_32 | BR_V)
 
 /* FLASH timing (0x0000_0c54) */
-#define CFG_OR_TIMING_FLASH    (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
+#define CFG_OR_TIMING_FLASH    (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
                                        OR_GPCM_SCY_5 | OR_GPCM_TRLX)
 
 #define CFG_PRELIM_OR_AM       0xc0000000      /* OR addr mask: 1 GiB */

diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index da323e8..a4d4d65 100644 (file)
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -28,39 +28,4 @@
 #define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
 #define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
 
-/*
- * Local Bus Controller - memory controller registers
- */
-#define BRx_V          0x00000001      /* Bank Valid                   */
-#define BRx_MS_GPCM    0x00000000      /* G.P.C.M. Machine Select      */
-#define BRx_MS_SDRAM   0x00000000      /* SDRAM Machine Select         */
-#define BRx_MS_UPMA    0x00000080      /* U.P.M.A Machine Select       */
-#define BRx_MS_UPMB    0x000000a0      /* U.P.M.B Machine Select       */
-#define BRx_MS_UPMC    0x000000c0      /* U.P.M.C Machine Select       */
-#define BRx_PS_8       0x00000800      /*  8 bit port size             */
-#define BRx_PS_32      0x00001800      /* 32 bit port size             */
-#define BRx_BA_MSK     0xffff8000      /* Base Address Mask            */
-
-#define ORxG_EAD       0x00000001      /* External addr latch delay    */
-#define ORxG_EHTR      0x00000002      /* Extended hold time on read   */
-#define ORxG_TRLX      0x00000004      /* Timing relaxed               */
-#define ORxG_SETA      0x00000008      /* External address termination */
-#define ORxG_SCY_10_CLK        0x000000a0      /* 10 clock cycles wait states  */
-#define ORxG_SCY_15_CLK        0x000000f0      /* 15 clock cycles wait states  */
-#define ORxG_XACS      0x00000100      /* Extra addr to CS setup       */
-#define ORxG_ACS_DIV2  0x00000600      /* CS is output 1/2 a clock later*/
-#define ORxG_CSNT      0x00000800      /* Chip Select Negation Time    */
-
-#define ORxU_BI                0x00000100      /* Burst Inhibit                */
-#define ORxU_AM_MSK    0xffff8000      /* Address Mask Mask            */
-
-#define MxMR_OP_NORM   0x00000000      /* Normal Operation             */
-#define MxMR_DSx_2_CYCL 0x00400000     /* 2 cycle Disable Period       */
-#define MxMR_OP_WARR   0x10000000      /* Write to Array               */
-#define MxMR_BSEL      0x80000000      /* Bus Select                   */
-
-/* helpers to convert values into an OR address mask (GPCM mode) */
-#define P2SZ_TO_AM(s)  ((~((s) - 1)) & 0xffff8000)     /* must be pow of 2 */
-#define MEG_TO_AM(m)   P2SZ_TO_AM((m) << 20)
-
 #endif /* __MPC85xx_H__ */