85xx: Use proper defines for PCI addresses

We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE.
While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only
be used for configuring the PCI ATMU.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S
index c495f1e..4c8dd0e 100644 (file)
--- a/board/freescale/mpc8540ads/init.S
+++ b/board/freescale/mpc8540ads/init.S
@@ -130,8 +130,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -139,8 +139,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded

diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index ab6a6f2..785576a 100644 (file)
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -48,7 +48,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        /* This is not so much the SDRAM map as it is the whole localbus map. */
        SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),

diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S
index 563ea2d..6e93fb0 100644 (file)
--- a/board/freescale/mpc8541cds/init.S
+++ b/board/freescale/mpc8541cds/init.S
@@ -130,8 +130,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -139,8 +139,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
@@ -148,8 +148,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 3, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
@@ -157,8 +157,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 4, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded

diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c
index a8aa4db..0ac223c 100644 (file)
--- a/board/freescale/mpc8541cds/law.c
+++ b/board/freescale/mpc8541cds/law.c
@@ -47,8 +47,8 @@
  */
 
 struct law_entry law_table[] = {
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-       SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
        /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */

diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 6920863..0ee53e2 100644 (file)
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -52,11 +52,11 @@
 
 struct law_entry law_table[] = {
 #ifdef CFG_PCI1_MEM_PHYS
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
 #endif
 #ifdef CFG_PCI2_MEM_PHYS
-       SET_LAW_ENTRY(4, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+       SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
        SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
 #endif
 #ifdef CFG_PCIE1_MEM_PHYS

diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S
index 563ea2d..6e93fb0 100644 (file)
--- a/board/freescale/mpc8555cds/init.S
+++ b/board/freescale/mpc8555cds/init.S
@@ -130,8 +130,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -139,8 +139,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
@@ -148,8 +148,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 3, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
@@ -157,8 +157,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 4, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded

diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c
index a8aa4db..0ac223c 100644 (file)
--- a/board/freescale/mpc8555cds/law.c
+++ b/board/freescale/mpc8555cds/law.c
@@ -47,8 +47,8 @@
  */
 
 struct law_entry law_table[] = {
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-       SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
        /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */

diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S
index 151b4f6..8ade9ca 100644 (file)
--- a/board/freescale/mpc8560ads/init.S
+++ b/board/freescale/mpc8560ads/init.S
@@ -131,8 +131,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -140,8 +140,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded

diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
index ab6a6f2..785576a 100644 (file)
--- a/board/freescale/mpc8560ads/law.c
+++ b/board/freescale/mpc8560ads/law.c
@@ -48,7 +48,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        /* This is not so much the SDRAM map as it is the whole localbus map. */
        SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),

diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
index 39819ab..c777eb1 100644 (file)
--- a/board/freescale/mpc8568mds/init.S
+++ b/board/freescale/mpc8568mds/init.S
@@ -140,8 +140,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLBe 3:      64M     Non-cacheable, guarded

diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index b35bbcd..5e96ea7 100644 (file)
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -50,8 +50,8 @@
  */
 
 struct law_entry law_table[] = {
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-       SET_LAW_ENTRY(3, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
        SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),

diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S
index adc5115..93654a5 100644 (file)
--- a/board/mpc8540eval/init.S
+++ b/board/mpc8540eval/init.S
@@ -115,8 +115,8 @@ tlb1_entry:
 
        .long FSL_BOOKE_MAS0(1,8,0)
        .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
        .long FSL_BOOKE_MAS0(1,9,0)
        .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)

diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c
index 4d603f0..273ec5c 100644 (file)
--- a/board/mpc8540eval/law.c
+++ b/board/mpc8540eval/law.c
@@ -45,7 +45,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
 #ifndef CONFIG_RAM_AS_FLASH
        SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 #endif

diff --git a/board/pm854/init.S b/board/pm854/init.S
index f6ea8b3..770daa0 100644 (file)
--- a/board/pm854/init.S
+++ b/board/pm854/init.S
@@ -131,8 +131,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -140,8 +140,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded

diff --git a/board/pm854/law.c b/board/pm854/law.c
index 65a4b59..cb6b37f 100644 (file)
--- a/board/pm854/law.c
+++ b/board/pm854/law.c
@@ -48,7 +48,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        /* This is not so much the SDRAM map as it is the whole localbus map. */
        SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),

diff --git a/board/pm856/init.S b/board/pm856/init.S
index f6ea8b3..770daa0 100644 (file)
--- a/board/pm856/init.S
+++ b/board/pm856/init.S
@@ -131,8 +131,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -140,8 +140,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded

diff --git a/board/pm856/law.c b/board/pm856/law.c
index 65a4b59..cb6b37f 100644 (file)
--- a/board/pm856/law.c
+++ b/board/pm856/law.c
@@ -48,7 +48,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        /* This is not so much the SDRAM map as it is the whole localbus map. */
        SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),

diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S
index 6696dd9..162c326 100644 (file)
--- a/board/sbc8548/init.S
+++ b/board/sbc8548/init.S
@@ -135,8 +135,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -144,8 +144,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0,
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0,
                        (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*

diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index 6bf4199..d903cdc 100644 (file)
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -48,7 +48,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
        /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
        SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),

diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S
index e149fbd..3baa506 100644 (file)
--- a/board/sbc8560/init.S
+++ b/board/sbc8560/init.S
@@ -103,8 +103,8 @@ tlb1_entry:
 
        .long FSL_BOOKE_MAS0(1,7,0)
        .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
        .long FSL_BOOKE_MAS0(1,15,0)

diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c
index d1c6dc2..e370853 100644 (file)
--- a/board/sbc8560/law.c
+++ b/board/sbc8560/law.c
@@ -53,7 +53,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
 };
 

diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S
index 9bc8dd6..8e1f16e 100644 (file)
--- a/board/stxgp3/init.S
+++ b/board/stxgp3/init.S
@@ -137,8 +137,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -146,8 +146,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded

diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c
index 6f215e1..312b3c5 100644 (file)
--- a/board/stxgp3/law.c
+++ b/board/stxgp3/law.c
@@ -48,7 +48,7 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        /* This is not so much the SDRAM map as it is the whole localbus map. */
        SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),

diff --git a/board/stxssa/init.S b/board/stxssa/init.S
index 0c4fb30..d747946 100644 (file)
--- a/board/stxssa/init.S
+++ b/board/stxssa/init.S
@@ -137,8 +137,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 1, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
@@ -146,8 +146,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
@@ -155,8 +155,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 3, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
@@ -164,8 +164,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 4, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded

diff --git a/board/stxssa/law.c b/board/stxssa/law.c
index 2969060..2b25292 100644 (file)
--- a/board/stxssa/law.c
+++ b/board/stxssa/law.c
@@ -49,8 +49,8 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-       SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+       SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
        SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
        /* Map the whole localbus, including flash and reset latch. */

diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S
index 1b25deb..f8b9fa2 100644 (file)
--- a/board/tqm85xx/init.S
+++ b/board/tqm85xx/init.S
@@ -119,8 +119,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 2, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
@@ -128,8 +128,8 @@ tlb1_entry:
         */
        .long FSL_BOOKE_MAS0(1, 3, 0)
        .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
-       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded

diff --git a/board/tqm85xx/law.c b/board/tqm85xx/law.c
index 1573e58..224af6c 100644 (file)
--- a/board/tqm85xx/law.c
+++ b/board/tqm85xx/law.c
@@ -45,7 +45,7 @@
 
 struct law_entry law_table[] = {
        SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
        SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
        SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),