ASoC: sun4i-i2s: Update registers for more channels

H6 expands the number of channels in each direction to 16, so the slot
number fields need to be expanded from 3 to 4 bits each.

R329/D1 expand that further by allowing each of the 16 slots to map to
any of 4 data pins. For TX, the configuration of each pin is
independent, so there is a copy of the mapping registers for each pin.
For RX, each of the 16 slots can map to only one pin, so the registers
were changed to add the pin selection inline with the channel mapping.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220203020116.12279-3-samuel@sholland.org
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 1e9116cd365e58c45badca758ff6aac3f1986681..7da8a16955a1b7d70b3c7011b0d9f8f1a7b75551 100644 (file)
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -115,9 +115,9 @@
 #define SUN8I_I2S_FIFO_TX_REG          0x20
 
 #define SUN8I_I2S_CHAN_CFG_REG         0x30
-#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK    GENMASK(6, 4)
+#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK    GENMASK(7, 4)
 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)   ((chan - 1) << 4)
-#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK    GENMASK(2, 0)
+#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK    GENMASK(3, 0)
 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)   (chan - 1)
 
 #define SUN8I_I2S_TX_CHAN_MAP_REG      0x44
@@ -138,13 +138,19 @@
 #define SUN50I_H6_I2S_TX_CHAN_EN_MASK          GENMASK(15, 0)
 #define SUN50I_H6_I2S_TX_CHAN_EN(num_chan)     (((1 << num_chan) - 1))
 
-#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
-#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
+#define SUN50I_H6_I2S_TX_CHAN_SEL_REG(pin)     (0x34 + 4 * (pin))
+#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG(pin)    (0x44 + 8 * (pin))
+#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG(pin)    (0x48 + 8 * (pin))
 
 #define SUN50I_H6_I2S_RX_CHAN_SEL_REG  0x64
 #define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
 #define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
 
+#define SUN50I_R329_I2S_RX_CHAN_MAP0_REG 0x68
+#define SUN50I_R329_I2S_RX_CHAN_MAP1_REG 0x6c
+#define SUN50I_R329_I2S_RX_CHAN_MAP2_REG 0x70
+#define SUN50I_R329_I2S_RX_CHAN_MAP3_REG 0x74
+
 struct sun4i_i2s;
 
 /**
@@ -523,13 +529,13 @@ static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
        unsigned int lrck_period;
 
        /* Map the channels for playback and capture */
-       regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98);
-       regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210);
+       regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98);
+       regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210);
        regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
        regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
 
        /* Configure the channels */
-       regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+       regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
                           SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
                           SUN50I_H6_I2S_TX_CHAN_SEL(channels));
        regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
@@ -563,7 +569,7 @@ static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
                           SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
                           SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
 
-       regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
+       regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0),
                           SUN50I_H6_I2S_TX_CHAN_EN_MASK,
                           SUN50I_H6_I2S_TX_CHAN_EN(channels));
 
@@ -1210,9 +1216,9 @@ static const struct reg_default sun50i_h6_i2s_reg_defaults[] = {
        { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
        { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
        { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
-       { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
-       { SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0x00000000 },
-       { SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x00000000 },
+       { SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), 0x00000000 },
+       { SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0x00000000 },
+       { SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x00000000 },
        { SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 },
        { SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 },
        { SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 },