if (!Subtarget->hasVInstructions())
return;
- assert((Node->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
- Node->getOpcode() == ISD::INTRINSIC_WO_CHAIN) &&
- "Unexpected opcode");
+ assert(Node->getOpcode() == ISD::INTRINSIC_WO_CHAIN && "Unexpected opcode");
SDLoc DL(Node);
MVT XLenVT = Subtarget->getXLenVT();
- bool HasChain = Node->getOpcode() == ISD::INTRINSIC_W_CHAIN;
- unsigned IntNoOffset = HasChain ? 1 : 0;
- unsigned IntNo = Node->getConstantOperandVal(IntNoOffset);
+ unsigned IntNo = Node->getConstantOperandVal(0);
assert((IntNo == Intrinsic::riscv_vsetvli ||
IntNo == Intrinsic::riscv_vsetvlimax) &&
"Unexpected vsetvli intrinsic");
bool VLMax = IntNo == Intrinsic::riscv_vsetvlimax;
- unsigned Offset = IntNoOffset + (VLMax ? 1 : 2);
+ unsigned Offset = (VLMax ? 1 : 2);
assert(Node->getNumOperands() == Offset + 2 &&
"Unexpected number of operands");
SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT);
SmallVector<EVT, 2> VTs = {XLenVT};
- if (HasChain)
- VTs.push_back(MVT::Other);
SDValue VLOperand;
unsigned Opcode = RISCV::PseudoVSETVLI;
VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
Opcode = RISCV::PseudoVSETVLIX0;
} else {
- VLOperand = Node->getOperand(IntNoOffset + 1);
+ VLOperand = Node->getOperand(1);
if (auto *C = dyn_cast<ConstantSDNode>(VLOperand)) {
uint64_t AVL = C->getZExtValue();
if (isUInt<5>(AVL)) {
SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT);
SmallVector<SDValue, 3> Ops = {VLImm, VTypeIOp};
- if (HasChain)
- Ops.push_back(Node->getOperand(0));
ReplaceNode(
Node, CurDAG->getMachineNode(RISCV::PseudoVSETIVLI, DL, VTs, Ops));
return;
}
SmallVector<SDValue, 3> Ops = {VLOperand, VTypeIOp};
- if (HasChain)
- Ops.push_back(Node->getOperand(0));
ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, VTs, Ops));
}