arm64: dts: imx93-11x11-evk: enable fec function

Enable FEC function for imx93-11x11-evk board.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index f37b6efa32aada144ed3b3d2b6dedce1067df1bf..91b196c49be1ac86439da9f462d2acfc24bb7062 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -55,6 +55,26 @@
        };
 };
 
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy2>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-frequency = <5000000>;
+
+               ethphy2: ethernet-phy@2 {
+                       reg = <2>;
+                       eee-broken-1000t;
+               };
+       };
+};
+
 &lpuart1 { /* console */
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -104,6 +124,25 @@
                >;
        };
 
+       pinctrl_fec: fecgrp {
+               fsl,pins = <
+                       MX93_PAD_ENET2_MDC__ENET1_MDC                   0x57e
+                       MX93_PAD_ENET2_MDIO__ENET1_MDIO                 0x57e
+                       MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0             0x57e
+                       MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1             0x57e
+                       MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2             0x57e
+                       MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3             0x57e
+                       MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC             0x5fe
+                       MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL       0x57e
+                       MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0             0x57e
+                       MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1             0x57e
+                       MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2             0x57e
+                       MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3             0x57e
+                       MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC             0x5fe
+                       MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL       0x57e
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX93_PAD_UART1_RXD__LPUART1_RX                  0x31e