usb: fix usb2 phy pll setting for g12a
authorYue Wang <yue.wang@amlogic.com>
Thu, 8 Feb 2018 11:59:30 +0000 (19:59 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Mon, 5 Mar 2018 07:34:30 +0000 (15:34 +0800)
PD#156734: usb: fix usb2 phy pll setting for g12a

Change-Id: I7b7ab2f9cddfa2b17e81f6691d2ba8f44f99555b
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
arch/arm64/boot/dts/amlogic/g12a_skt.dts
arch/arm64/boot/dts/amlogic/mesong12a.dtsi
drivers/amlogic/usb/phy/phy-aml-new-usb2-v2.c
include/linux/amlogic/usb-v2.h

index 5c426c5..3492ed4 100644 (file)
                       0x0 0xFF800000 0x0 0x400>;
        };
 
-       dwc3: dwc3@ff500000 {
-               compatible = "synopsys, dwc3";
-               status = "okay";
-               reg = <0x0 0xff500000 0x0 0x100000>;
-               interrupts = <0 30 4>;
-               usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
-               cpu-type = "gxl";
-               clock-src = "usb3.0";
-               clocks = <&clkc CLKID_USB_GENERAL>;
-               clock-names = "dwc_general";
-       };
-
-       usb2_phy_v2: usb2phy@ffe09000 {
-               compatible = "amlogic, amlogic-new-usb2-v2";
-               status = "okay";
-               portnum = <2>;
-               reg = <0x0 0xffe09000 0x0 0x80
-                               0x0 0xffd01008 0x0 0x4
-                               0x0 0xff636000 0x0 0x2000
-                               0x0 0xff63a000 0x0 0x2000>;
-       };
-
-       usb3_phy_v2: usb3phy@ffe09080 {
-               compatible = "amlogic, amlogic-new-usb3-v2";
-               status = "okay";
-               portnum = <0>;
-               reg = <0x0 0xffe09080 0x0 0x20>;
-               phy-reg = <0xff646000>;
-               phy-reg-size = <0x4>;
-               usb2-phy-reg = <0xffe09000>;
-               usb2-phy-reg-size = <0x80>;
-               interrupts = <0 16 4>;
-               otg = <1>;
-               clocks = <&clkc CLKID_PCIE_PLL>;
-               clock-names = "pcie_refpll";
-               gpio-vbus-power = "GPIOH_6";
-               gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
-       };
-
-       dwc2_a {
-               compatible = "amlogic, dwc2";
-               device_name = "dwc2_a";
-               reg = <0x0 0xff400000 0x0 0x40000>;
-               status = "okay";
-               interrupts = <0 31 4>;
-               pl-periph-id = <0>; /** lm name */
-               clock-src = "usb0"; /** clock src */
-               port-id = <0>;  /** ref to mach/usb.h */
-               port-type = <2>;        /** 0: otg, 1: host, 2: slave */
-               port-speed = <0>; /** 0: default, high, 1: full */
-               port-config = <0>; /** 0: default */
-               /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/
-               port-dma = <0>;
-               port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
-               usb-fifo = <728>;
-               cpu-type = "v2";
-               /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/
-               controller-type = <3>;
-               phy-reg = <0xffe09000>;
-               phy-reg-size = <0xa0>;
-               /** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/
-               phy-interface = <0x0>;
-               clocks = <&clkc CLKID_USB_GENERAL
-                                       &clkc CLKID_USB1_TO_DDR>;
-               clock-names = "usb_general",
-                                       "usb1";
-       };
-
        canvas{
                compatible = "amlogic, meson, canvas";
                dev_name = "amlogic-canvas";
        status = "okay";
 };
 
+&dwc3 {
+       status = "okay";
+};
+
+&usb2_phy_v2 {
+       status = "okay";
+       portnum = <2>;
+};
+
+&usb3_phy_v2 {
+       status = "okay";
+       portnum = <0>;
+       otg = <1>;
+       gpio-vbus-power = "GPIOH_6";
+       gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&dwc2_a {
+       status = "okay";
+       /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/
+       controller-type = <3>;
+};
+
index 986f467..5312bf2 100644 (file)
                };
        };
 
+       dwc3: dwc3@ff500000 {
+               compatible = "synopsys, dwc3";
+               status = "disable";
+               reg = <0x0 0xff500000 0x0 0x100000>;
+               interrupts = <0 30 4>;
+               usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>;
+               cpu-type = "gxl";
+               clock-src = "usb3.0";
+               clocks = <&clkc CLKID_USB_GENERAL>;
+               clock-names = "dwc_general";
+       };
+
+       usb2_phy_v2: usb2phy@ffe09000 {
+               compatible = "amlogic, amlogic-new-usb2-v2";
+               status = "disable";
+               reg = <0x0 0xffe09000 0x0 0x80
+                               0x0 0xffd01008 0x0 0x4
+                               0x0 0xff636000 0x0 0x2000
+                               0x0 0xff63a000 0x0 0x2000>;
+               pll-setting-1 = <0x09400414>;
+               pll-setting-2 = <0x927E0000>;
+               pll-setting-3 = <0xac5f49e5>;
+       };
+
+       usb3_phy_v2: usb3phy@ffe09080 {
+               compatible = "amlogic, amlogic-new-usb3-v2";
+               status = "disable";
+               reg = <0x0 0xffe09080 0x0 0x20>;
+               phy-reg = <0xff646000>;
+               phy-reg-size = <0x4>;
+               usb2-phy-reg = <0xffe09000>;
+               usb2-phy-reg-size = <0x80>;
+               interrupts = <0 16 4>;
+               clocks = <&clkc CLKID_PCIE_PLL>;
+               clock-names = "pcie_refpll";
+       };
+
+       dwc2_a: dwc2@ff400000 {
+               compatible = "amlogic, dwc2";
+               status = "disable";
+               device_name = "dwc2_a";
+               reg = <0x0 0xff400000 0x0 0x40000>;
+               interrupts = <0 31 4>;
+               pl-periph-id = <0>; /** lm name */
+               clock-src = "usb0"; /** clock src */
+               port-id = <0>;  /** ref to mach/usb.h */
+               port-type = <2>;        /** 0: otg, 1: host, 2: slave */
+               port-speed = <0>; /** 0: default, high, 1: full */
+               port-config = <0>; /** 0: default */
+               /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/
+               port-dma = <0>;
+               port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/
+               usb-fifo = <728>;
+               cpu-type = "v2";
+               phy-reg = <0xffe09000>;
+               phy-reg-size = <0xa0>;
+               /** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/
+               phy-interface = <0x0>;
+               clocks = <&clkc CLKID_USB_GENERAL
+                                       &clkc CLKID_USB1_TO_DDR>;
+               clock-names = "usb_general",
+                                       "usb1";
+       };
+
        wdt: watchdog@0xffd0f0d0 {
                compatible = "amlogic,meson-g12a-wdt";
                status = "okay";
index 77dae47..86eaa35 100644 (file)
 #include <linux/amlogic/usb-v2.h>
 #include "phy-aml-new-usb-v2.h"
 
-void set_usb_pll(void __iomem  *reg)
+void set_usb_pll(struct amlogic_usb_v2 *phy, void __iomem      *reg)
 {
        /* TO DO set usb  PLL */
-       writel(0x39400414, reg + 0x40);
-       writel(0x927E0000, reg + 0x44);
-       writel(0xAD5B29E9, reg + 0x48);
+       writel((0x30000000 | (phy->pll_setting[0])), reg + 0x40);
+       writel(phy->pll_setting[1], reg + 0x44);
+       writel(phy->pll_setting[2], reg + 0x48);
        udelay(100);
-       writel(0x19400414, reg + 0x40);
+       writel((0x10000000 | (phy->pll_setting[0])), reg + 0x40);
 }
 
 static int amlogic_new_usb2_init(struct usb_phy *x)
@@ -103,11 +103,12 @@ static int amlogic_new_usb2_init(struct usb_phy *x)
                        cnt++;
                        udelay(5);
                }
-
-               /* step 7: pll setting */
-               set_usb_pll(phy->phy_cfg[i]);
        }
 
+       /* step 7: pll setting */
+       for (i = 0; i < phy->portnum; i++)
+               set_usb_pll(phy, phy->phy_cfg[i]);
+
        return 0;
 }
 
@@ -147,6 +148,8 @@ static int amlogic_new_usb2_probe(struct platform_device *pdev)
        int portnum = 0;
        const void *prop;
        int i = 0;
+       u32 retval;
+       u32 pll_setting[3];
 
        prop = of_get_property(dev->of_node, "portnum", NULL);
        if (prop)
@@ -185,6 +188,21 @@ static int amlogic_new_usb2_probe(struct platform_device *pdev)
        if (!phy)
                return -ENOMEM;
 
+       retval = of_property_read_u32(dev->of_node,
+               "pll-setting-1", &(pll_setting[0]));
+       if (retval < 0)
+               return -EINVAL;
+
+       retval = of_property_read_u32(dev->of_node,
+               "pll-setting-2", &(pll_setting[1]));
+       if (retval < 0)
+               return -EINVAL;
+
+       retval = of_property_read_u32(dev->of_node,
+               "pll-setting-3", &(pll_setting[2]));
+       if (retval < 0)
+               return -EINVAL;
+
        dev_info(&pdev->dev, "USB2 phy probe:phy_mem:0x%lx, iomap phy_base:0x%lx\n",
                        (unsigned long)phy_mem->start, (unsigned long)phy_base);
 
@@ -199,6 +217,9 @@ static int amlogic_new_usb2_probe(struct platform_device *pdev)
        phy->phy.set_suspend    = amlogic_new_usb2_suspend;
        phy->phy.shutdown       = amlogic_new_usb2phy_shutdown;
        phy->phy.type           = USB_PHY_TYPE_USB2;
+       phy->pll_setting[0] = pll_setting[0];
+       phy->pll_setting[1] = pll_setting[1];
+       phy->pll_setting[2] = pll_setting[2];
        for (i = 0; i < portnum; i++)
                phy->phy_cfg[i] = phy_cfg_base[i];
 
index 77c8c22..09f833c 100644 (file)
@@ -165,6 +165,7 @@ struct amlogic_usb_v2 {
        void __iomem    *phy_cfg[4];
        void __iomem    *phy3_cfg;
        void __iomem    *usb2_phy_cfg;
+       u32 pll_setting[3];
        /* Set VBus Power though GPIO */
        int vbus_power_pin;
        int vbus_power_pin_work_mask;