radeon/video: always use the reusable buffer pool
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Sat, 23 Apr 2016 03:50:19 +0000 (22:50 -0500)
committerNicolai Hähnle <nicolai.haehnle@amd.com>
Wed, 27 Apr 2016 16:16:41 +0000 (11:16 -0500)
A semantic error was introduced in a past refactoring that caused the bind
parameter to be passed into the use_reusable_pool parameter of buffer_create.
Since this clearly makes no sense, and there is no clear reason why the
cache _shouldn't_ be used, just use the cache always.

Cc: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/r600/r600_uvd.c
src/gallium/drivers/radeon/radeon_video.c
src/gallium/drivers/radeon/radeon_video.h
src/gallium/drivers/radeonsi/si_uvd.c

index 0c92834..628ba2a 100644 (file)
@@ -115,7 +115,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
                surfaces[i] = &resources[i]->surface;
        }
 
-       rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
+       rvid_join_surfaces(ctx->b.ws, pbs, surfaces);
 
        for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
                if (!resources[i])
index 24b0eed..8dd32ea 100644 (file)
@@ -130,7 +130,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
  * join surfaces into the same buffer with identical tiling params
  * sumup their sizes and replace the backend buffers with a single bo
  */
-void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+void rvid_join_surfaces(struct radeon_winsys* ws,
                        struct pb_buffer** buffers[VL_NUM_COMPONENTS],
                        struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 {
@@ -185,7 +185,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
        /* TODO: 2D tiling workaround */
        alignment *= 2;
 
-       pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM, 0);
+       pb = ws->buffer_create(ws, size, alignment, TRUE, RADEON_DOMAIN_VRAM, 0);
        if (!pb)
                return;
 
index c9ee67f..39305b4 100644 (file)
@@ -66,7 +66,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
 
 /* join surfaces into the same buffer with identical tiling params
    sumup their sizes and replace the backend buffers with a single bo */
-void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+void rvid_join_surfaces(struct radeon_winsys* ws,
                         struct pb_buffer** buffers[VL_NUM_COMPONENTS],
                         struct radeon_surf *surfaces[VL_NUM_COMPONENTS]);
 
index 95bfecd..8c3e5fd 100644 (file)
@@ -97,7 +97,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
                pbs[i] = &resources[i]->resource.buf;
        }
 
-       rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
+       rvid_join_surfaces(ctx->b.ws, pbs, surfaces);
 
        for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
                if (!resources[i])