drm/amd/display: Drop uncessary OTG lock check
authorRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tue, 27 Sep 2022 22:30:08 +0000 (18:30 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 10 Oct 2022 21:32:55 +0000 (17:32 -0400)
The OTG_MASTER_UPDATE_LOCK_SEL is used for GSL and OTGs in the same
group for selecting the OTG_MASTER_UPDATE_LOCK from the same OTG. At
some point, it a check was added to see if OTG is running or not, which
is not necessary, and for this reason, this commit dropped that check.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

index dca8a1446120b2ae19fe88a47a1496f037e833ae..33d7802187900866958df55bfd39f5627b83302f 100644 (file)
@@ -646,13 +646,6 @@ uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
 void optc1_lock(struct timing_generator *optc)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
-       uint32_t regval = 0;
-
-       regval = REG_READ(OTG_CONTROL);
-
-       /* otg is not running, do not need to be locked */
-       if ((regval & 0x1) == 0x0)
-               return;
 
        REG_SET(OTG_GLOBAL_CONTROL0, 0,
                        OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
@@ -660,12 +653,10 @@ void optc1_lock(struct timing_generator *optc)
                        OTG_MASTER_UPDATE_LOCK, 1);
 
        /* Should be fast, status does not update on maximus */
-       if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
-
+       if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
                REG_WAIT(OTG_MASTER_UPDATE_LOCK,
                                UPDATE_LOCK_STATUS, 1,
                                1, 10);
-       }
 }
 
 void optc1_unlock(struct timing_generator *optc)