// Widen Vector Result Promotion.
void WidenVectorResult(SDNode *N, unsigned ResNo);
SDValue WidenVecRes_MERGE_VALUES(SDNode* N, unsigned ResNo);
+ SDValue WidenVecRes_AssertZext(SDNode* N);
SDValue WidenVecRes_BITCAST(SDNode* N);
SDValue WidenVecRes_BUILD_VECTOR(SDNode* N);
SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N);
// Generic Result Splitting.
void SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
SDValue &Lo, SDValue &Hi);
+ void SplitVecRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitRes_ARITH_FENCE (SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitRes_Select (SDNode *N, SDValue &Lo, SDValue &Hi);
void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
Hi = DAG.getUNDEF(HiVT);
}
+void DAGTypeLegalizer::SplitVecRes_AssertZext(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue L, H;
+ SDLoc dl(N);
+ GetSplitOp(N->getOperand(0), L, H);
+
+ Lo = DAG.getNode(ISD::AssertZext, dl, L.getValueType(), L, N->getOperand(1));
+ Hi = DAG.getNode(ISD::AssertZext, dl, H.getValueType(), H, N->getOperand(1));
+}
+
void DAGTypeLegalizer::SplitRes_FREEZE(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue L, H;
SDLoc dl(N);
"operator!\n");
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
+ case ISD::AssertZext: SplitVecRes_AssertZext(N, Lo, Hi); break;
case ISD::VSELECT:
case ISD::SELECT:
case ISD::VP_MERGE:
llvm_unreachable("Do not know how to widen the result of this operator!");
case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
+ case ISD::AssertZext: Res = WidenVecRes_AssertZext(N); break;
case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
return DAG.getBuildVector(WidenVT, dl, Ops);
}
+SDValue DAGTypeLegalizer::WidenVecRes_AssertZext(SDNode *N) {
+ SDValue InOp = ModifyToType(
+ N->getOperand(0),
+ TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)), true);
+ return DAG.getNode(ISD::AssertZext, SDLoc(N), InOp.getValueType(), InOp,
+ N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
SDValue InOp = GetWidenedVector(N->getOperand(0));
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s
+
+define i64 @split_assertzext(ptr %x) nounwind {
+; CHECK-LABEL: split_assertzext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: callq test@PLT
+; CHECK-NEXT: vextracti32x4 $3, %zmm1, %xmm0
+; CHECK-NEXT: vpextrq $1, %xmm0, %rax
+; CHECK-NEXT: popq %rcx
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %e = call <16 x i64> @test(), !range !0
+ %d = extractelement <16 x i64> %e, i32 15
+ ret i64 %d
+}
+
+define i64 @widen_assertzext(ptr %x) nounwind {
+; CHECK-LABEL: widen_assertzext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rax
+; CHECK-NEXT: callq test2@PLT
+; CHECK-NEXT: movb $127, %al
+; CHECK-NEXT: kmovw %eax, %k1
+; CHECK-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT: vmovq %xmm0, %rax
+; CHECK-NEXT: popq %rcx
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %e = call <7 x i64> @test2(), !range !0
+ %d = extractelement <7 x i64> %e, i32 6
+ ret i64 %d
+}
+
+declare <16 x i64> @test()
+declare <7 x i64> @test2()
+!0 = !{ i64 0, i64 2 }