drm/nouveau/gr/gm200: modify the mask when copying mmu settings from fb
authorBen Skeggs <bskeggs@redhat.com>
Thu, 14 Apr 2016 04:41:52 +0000 (14:41 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 20 May 2016 04:43:04 +0000 (14:43 +1000)
Appears to more closely match what RM does.

For GM20B, now also copying bit 12 from NV_PFB_MMU_CTRL as upcoming
changes will require it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c

index 962366f..e2384c4 100644 (file)
@@ -36,10 +36,8 @@ static void
 gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
 {
        struct nvkm_device *device = gr->base.engine.subdev.device;
-       u32 tmp;
 
-       tmp = nvkm_rd32(device, 0x100c80); /*XXX: mask? */
-       nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff));
+       nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff);
        nvkm_wr32(device, 0x418890, 0x00000000);
        nvkm_wr32(device, 0x418894, 0x00000000);
 
index 1281a9c..f1ea0ba 100644 (file)
@@ -42,7 +42,7 @@ gm20b_gr_init_gpc_mmu(struct gf100_gr *gr)
        }
 
        val = nvkm_rd32(device, 0x100c80);
-       val &= 0xf000087f;
+       val &= 0xf000187f;
        nvkm_wr32(device, 0x418880, val);
        nvkm_wr32(device, 0x418890, 0);
        nvkm_wr32(device, 0x418894, 0);