* gas/i860/dual01.{s,d}: New files.
* gas/i860/dual02-err.{s,l}: New files.
* gas/i860/dual03.{s,d}: New files.
* gas/i860/i860.exp: Execute the above new tests.
* gas/i860/README.i860: Update.
+2003-08-03 Jason Eckhardt <jle@rice.edu>
+
+ * gas/i860/dual01.{s,d}: New files.
+ * gas/i860/dual02-err.{s,l}: New files.
+ * gas/i860/dual03.{s,d}: New files.
+ * gas/i860/i860.exp: Execute the above new tests.
+ * gas/i860/README.i860: Update.
+
2003-08-02 Alan Modra <amodra@bigpond.net.au>
* gas/d10v/address-001.d: Adjust for objdump -d change.
---------------------------------------------------
This is a simple testsuite for the i860 assembler. It currently
-consists of testcases for checking that every instruction is
-parsed correctly and that correct object code is generated.
+consists mostly of testcases for checking that every instruction is
+parsed correctly and that correct object code is generated (these
+are called "blah.s"). The files called "blah-err.s" test for error
+conditions.
-It includes testcases for the base i860XR instruction set as well
+The suite includes testcases for the base i860XR instruction set as well
as the enhanced i860XP instructions and control registers.
The expected results files were generated using the UNIX System V/i860
TODO:
- Relocation testing is basically non-existent.
- pst.d (pixel store) is the only instruction with no testcase.
- - Tests for dual instruction mode: alignment of a dual mode pair,
- check that dual mode has a proper pair (FLOP/integer) of instructions,
- known gas defect when handling the d.fnop, etc.
- - All current testcases use the default AT&T/SVR4 syntax; a few simple
- tests of the Intel syntax should be added to prevent bitrot.
+ - More tests for dual instruction mode: check that dual mode has a
+ proper pair (FLOP/core) of instructions, and other error conditions.
+ - Most current testcases use the default AT&T/SVR4 syntax; a few simple
+ tests of the Intel syntax should be added to prevent bitrot (including
+ relocatable expression syntax, etc). Test file dual03.s uses Intel
+ syntax lightly (i.e., register names without '%' prefix).
Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help.
+Known failures:
+ - dual01.s: GAS mishandles d.fnop (dual bit erroneously set on next
+ instruction).
+ - dual02-err.s: GAS currently doesn't check that dual mode pairs
+ are properly aligned.
+
--- /dev/null
+#as:
+#objdump: -d
+#name: i860 dual01
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+ 0: 00 00 00 a0 shl %r0,%r0,%r0
+ 4: 00 00 00 a0 shl %r0,%r0,%r0
+ 8: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12
+ c: 00 28 c6 90 adds %r5,%r6,%r6
+ 10: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12
+ 14: 10 00 58 25 fld.d 16\(%r10\),%f24
+ 18: 00 02 00 b0 d.shrd %r0,%r0,%r0
+ 1c: 08 00 48 25 fld.d 8\(%r10\),%f8
+ 20: 00 02 00 b0 d.shrd %r0,%r0,%r0
+ 24: 00 00 50 25 fld.d 0\(%r10\),%f16
+ 28: 00 00 00 a0 shl %r0,%r0,%r0
+ 2c: 00 00 00 a0 shl %r0,%r0,%r0
--- /dev/null
+# Test fnop's dual bit (all other floating point operations have their dual
+# bit tested in their individual test files).
+
+ .text
+ .align 8
+ nop
+ nop
+ d.pfadd.dd %f8,%f10,%f12
+ adds %r5,%r6,%r6
+ d.pfadd.dd %f8,%f10,%f12
+ fld.d 16(%r10),%f24
+ d.fnop
+ fld.d 8(%r10),%f8
+ d.fnop
+ fld.d 0(%r10),%f16
+ nop
+ nop
--- /dev/null
+.*: Assembler messages:
+.*:7: Error: FLOP with 'd\.' prefix must be 8-byte aligned
--- /dev/null
+# Dual-mode pairs must be aligned on an 8-byte boundary. This tests
+# that an error is reported if not properly aligned.
+
+ .text
+ .align 8
+ nop
+ d.fadd.ss %f3,%f5,%f7
+ addu %r4,%r5,%r6
+
--- /dev/null
+#as: -mintel-syntax
+#objdump: -d
+#name: i860 dual03
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <L1-0x20>:
+ 0: 00 00 14 22 fld.d %r0\(%r16\),%f20
+ 4: fe ff 15 94 adds -2,%r0,%r21
+ 8: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
+ c: fa ff 31 96 adds -6,%r17,%r17
+ 10: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
+ 14: 02 a8 20 b6 bla %r21,%r17,0x00000020 // 20 <L1>
+ 18: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0
+ 1c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22
+
+00000020 <L1>:
+ 20: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
+ 24: 06 a8 20 b6 bla %r21,%r17,0x00000040 // 40 <L2>
+ 28: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
+ 2c: 09 00 14 26 fld.d 8\(%r16\)\+\+,%f20
+ 30: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
+ 34: 0a 00 00 68 br 0x00000060 // 60 <S>
+ 38: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
+ 3c: 00 00 00 a0 shl %r0,%r0,%r0
+
+00000040 <L2>:
+ 40: 30 b6 de 4b d.pfadd.ss %f22,%f30,%f30
+ 44: f6 af 3f b6 bla %r21,%r17,0x00000020 // 20 <L1>
+ 48: 30 be ff 4b d.pfadd.ss %f23,%f31,%f31
+ 4c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22
+ 50: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30
+ 54: 00 00 00 a0 shl %r0,%r0,%r0
+ 58: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31
+ 5c: 00 00 00 a0 shl %r0,%r0,%r0
+
+00000060 <S>:
+ 60: 30 b4 de 4b pfadd.ss %f22,%f30,%f30
+ 64: fc ff 15 94 adds -4,%r0,%r21
+ 68: 30 bc ff 4b pfadd.ss %f23,%f31,%f31
+ 6c: 02 a8 20 5a bte %r21,%r17,0x00000078 // 78 <DONE>
+ 70: 0b 00 14 26 fld.l 8\(%r16\)\+\+,%f20
+ 74: 30 a4 de 4b pfadd.ss %f20,%f30,%f30
+
+00000078 <DONE>:
+ 78: 30 04 1e 48 pfadd.ss %f0,%f0,%f30
+ 7c: 30 f4 ff 4b pfadd.ss %f30,%f31,%f31
+ 80: 30 04 1e 48 pfadd.ss %f0,%f0,%f30
+ 84: 30 04 00 48 pfadd.ss %f0,%f0,%f0
+ 88: 30 04 1f 48 pfadd.ss %f0,%f0,%f31
+ 8c: 30 f0 f0 4b fadd.ss %f30,%f31,%f16
--- /dev/null
+// A larger dual-mode test, from the programmer's reference manual.
+// This uses Intel syntax, as in the manual.
+
+// Single-precision vector sum
+ fld.d r0(r16),f20
+ mov -2,r21
+ d.pfadd.ss f0,f0,f0
+ adds -6,r17,r17
+ d.pfadd.ss f0,f0,f0
+ bla r21,r17,L1
+ d.pfadd.ss f0,f0,f0
+ fld.d 8(r16)++,f22
+L1:
+ d.pfadd.ss f20,f30,f30
+ bla r21,r17,L2
+ d.pfadd.ss f21,f31,f31
+ fld.d 8(r16)++,f20
+ d.pfadd.ss f20,f30,f30
+ br S
+ d.pfadd.ss f21,f31,f31
+ nop
+L2:
+ d.pfadd.ss f22,f30,f30
+ bla r21,r17,L1
+ d.pfadd.ss f23,f31,f31
+ fld.d 8(r16)++,f22
+ d.pfadd.ss f20,f30,f30
+ nop
+ d.pfadd.ss f21,f31,f31
+ nop
+S:
+ pfadd.ss f22,f30,f30
+ mov -4,r21
+ pfadd.ss f23,f31,f31
+ bte r21,r17,DONE
+ fld.l 8(r16)++,f20
+ pfadd.ss f20,f30,f30
+DONE:
+ pfadd.ss f0,f0,f30
+ pfadd.ss f30,f31,f31
+ pfadd.ss f0,f0,f30
+ pfadd.ss f0,f0,f0
+ pfadd.ss f0,f0,f31
+ fadd.ss f30,f31,f16
+
+
# i860 assembler testsuite.
-if [istarget i860-*-*] {
- foreach file [lsort [glob -nocomplain -- $srcdir/$subdir/*.s]] {
- set file [file tail $file]
- set file [file rootname $file]
- run_dump_test "$file"
+proc run_list_test { name opts } {
+ global srcdir subdir
+ set testname "i860 $name"
+ set file $srcdir/$subdir/$name
+ gas_run ${name}.s $opts ">&dump.out"
+ if { [regexp_diff "dump.out" "${file}.l"] } then {
+ fail $testname
+ verbose "output is [file_contents "dump.out"]" 2
+ return
}
-}
\ No newline at end of file
+ pass $testname
+}
+
+if [istarget i860-*-*] {
+ run_dump_test "bitwise"
+ run_dump_test "branch"
+ run_dump_test "bte"
+ run_dump_test "dual01"
+ run_list_test "dual02-err" ""
+ run_dump_test "dual03"
+ run_dump_test "fldst01"
+ run_dump_test "fldst02"
+ run_dump_test "fldst03"
+ run_dump_test "fldst04"
+ run_dump_test "fldst05"
+ run_dump_test "fldst06"
+ run_dump_test "fldst07"
+ run_dump_test "fldst08"
+ run_dump_test "float01"
+ run_dump_test "float02"
+ run_dump_test "float03"
+ run_dump_test "float04"
+ run_dump_test "form"
+ run_dump_test "iarith"
+ run_dump_test "ldst01"
+ run_dump_test "ldst02"
+ run_dump_test "ldst03"
+ run_dump_test "ldst04"
+ run_dump_test "ldst05"
+ run_dump_test "ldst06"
+ run_dump_test "pfam"
+ run_dump_test "pfmam"
+ run_dump_test "pfmsm"
+ run_dump_test "pfsm"
+ run_dump_test "regress01"
+ run_dump_test "shift"
+ run_dump_test "simd"
+ run_dump_test "system"
+ run_dump_test "xp"
+}
+
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