drm/amdgpu: add psp support for navy_flounder

Currently skip ASD FW loading and ih reroute per
sienna_cichlid.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 6e41d89..aa80cf7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -99,6 +99,7 @@ static int psp_early_init(void *handle)
        case CHIP_NAVI14:
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                psp_v11_0_set_psp_funcs(psp);
                psp->autoload_supported = true;
                break;
@@ -498,7 +499,9 @@ static int psp_asd_load(struct psp_context *psp)
         * add workaround to bypass it for sriov now.
         * TODO: add version check to make it common
         */
-       if (amdgpu_sriov_vf(psp->adev) || (psp->adev->asic_type == CHIP_SIENNA_CICHLID))
+       if (amdgpu_sriov_vf(psp->adev) ||
+           (psp->adev->asic_type == CHIP_SIENNA_CICHLID) ||
+           (psp->adev->asic_type == CHIP_NAVY_FLOUNDER))
                return 0;
 
        cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
@@ -1763,7 +1766,8 @@ static int psp_np_fw_load(struct psp_context *psp)
                        continue;
 
                if (psp->autoload_supported &&
-                   adev->asic_type == CHIP_SIENNA_CICHLID &&
+                   (adev->asic_type == CHIP_SIENNA_CICHLID ||
+                    adev->asic_type == CHIP_NAVY_FLOUNDER) &&
                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
                     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
                     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 4233862..77f9981 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_asd.bin");
+MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
+MODULE_FIRMWARE("amdgpu/navy_flounder_asd.bin");
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS          0x3010024
@@ -100,6 +102,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
        case CHIP_SIENNA_CICHLID:
                chip_name = "sienna_cichlid";
                break;
+       case CHIP_NAVY_FLOUNDER:
+               chip_name = "navy_flounder";
+               break;
        default:
                BUG();
        }
@@ -108,7 +113,8 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
        if (err)
                return err;
 
-       if (adev->asic_type != CHIP_SIENNA_CICHLID) {
+       if (adev->asic_type != CHIP_SIENNA_CICHLID &&
+           adev->asic_type != CHIP_NAVY_FLOUNDER) {
                err = psp_init_asd_microcode(psp, chip_name);
                if (err)
                        return err;
@@ -173,6 +179,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
                }
                break;
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                break;
        default:
                BUG();
@@ -397,7 +404,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
        struct amdgpu_device *adev = psp->adev;
 
        if ((!amdgpu_sriov_vf(adev)) &&
-           (adev->asic_type != CHIP_SIENNA_CICHLID))
+           (adev->asic_type != CHIP_SIENNA_CICHLID) &&
+           (adev->asic_type != CHIP_NAVY_FLOUNDER))
                psp_v11_0_reroute_ih(psp);
 
        ring = &psp->km_ring;