arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash

Enable mt25qu512a flash connected to QSPI0.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211121234906.9602-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 3bea97f..28af633 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -186,6 +186,18 @@
                line-name = "gpio_sd0_pwr_en";
        };
 
+       qspi0_pins: qspi0 {
+               qspi0-data {
+                       pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
+                       power-source = <1800>;
+               };
+
+               qspi0-ctrl {
+                       pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
+                       power-source = <1800>;
+               };
+       };
+
        /*
         * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
         * The below switch logic can be used to select the device between
@@ -251,6 +263,34 @@
        };
 };
 
+&sbc {
+       pinctrl-0 = <&qspi0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       flash@0 {
+               compatible = "micron,mt25qu512a", "jedec,spi-nor";
+               reg = <0>;
+               m25p,fast-read;
+               spi-max-frequency = <50000000>;
+               spi-rx-bus-width = <4>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       boot@0 {
+                               reg = <0x00000000 0x2000000>;
+                               read-only;
+                       };
+                       user@2000000 {
+                               reg = <0x2000000 0x2000000>;
+                       };
+               };
+       };
+};
+
 #if SDHI
 &sdhi0 {
        pinctrl-0 = <&sdhi0_pins>;