drm/amd/display: correct static_screen_event_mask

[why]
HW register bit define changed.

Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 165c920..4226a05 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -623,3 +623,43 @@ void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
        if (hws->ctx->dc->debug.hpo_optimization)
                REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
 }
+void dcn31_set_drr(struct pipe_ctx **pipe_ctx,
+               int num_pipes, struct dc_crtc_timing_adjust adjust)
+{
+       int i = 0;
+       struct drr_params params = {0};
+       unsigned int event_triggers = 0x2;/*Bit[1]: OTG_TRIG_A*/
+       unsigned int num_frames = 2;
+       params.vertical_total_max = adjust.v_total_max;
+       params.vertical_total_min = adjust.v_total_min;
+       params.vertical_total_mid = adjust.v_total_mid;
+       params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
+       for (i = 0; i < num_pipes; i++) {
+               if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
+                       if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
+                               pipe_ctx[i]->stream_res.tg->funcs->set_drr(
+                                       pipe_ctx[i]->stream_res.tg, &params);
+                       if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
+                               if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
+                                       pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
+                                               pipe_ctx[i]->stream_res.tg,
+                                               event_triggers, num_frames);
+               }
+       }
+}
+void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+               int num_pipes, const struct dc_static_screen_params *params)
+{
+       unsigned int i;
+       unsigned int triggers = 0;
+       if (params->triggers.surface_update)
+               triggers |= 0x600;/*bit 9 and bit10 : 110 0000 0000*/
+       if (params->triggers.cursor_update)
+               triggers |= 0x10;/*bit4*/
+       if (params->triggers.force_trigger)
+               triggers |= 0x1;
+       for (i = 0; i < num_pipes; i++)
+               pipe_ctx[i]->stream_res.tg->funcs->
+                       set_static_screen_control(pipe_ctx[i]->stream_res.tg,
+                                       triggers, params->num_frames);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
index edfc01d..e7e03a8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
@@ -56,4 +56,8 @@ bool dcn31_is_abm_supported(struct dc *dc,
 void dcn31_init_pipes(struct dc *dc, struct dc_state *context);
 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
 
+void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+               int num_pipes, const struct dc_static_screen_params *params);
+void dcn31_set_drr(struct pipe_ctx **pipe_ctx,
+               int num_pipes, struct dc_crtc_timing_adjust adjust);
 #endif /* __DC_HWSS_DCN31_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index 3a32810..7c2da70 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -64,9 +64,9 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
        .prepare_bandwidth = dcn20_prepare_bandwidth,
        .optimize_bandwidth = dcn20_optimize_bandwidth,
        .update_bandwidth = dcn20_update_bandwidth,
-       .set_drr = dcn10_set_drr,
+       .set_drr = dcn31_set_drr,
        .get_position = dcn10_get_position,
-       .set_static_screen_control = dcn10_set_static_screen_control,
+       .set_static_screen_control = dcn31_set_static_screen_control,
        .setup_stereo = dcn10_setup_stereo,
        .set_avmute = dcn30_set_avmute,
        .log_hw_state = dcn10_log_hw_state,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
index 63a677c..fe449f7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -40,6 +40,7 @@
 #define FN(reg_name, field_name) \
        optc1->tg_shift->field_name, optc1->tg_mask->field_name
 
+#define STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN 0x2000 /*bit 13*/
 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
                struct dc_crtc_timing *timing)
 {
@@ -231,6 +232,32 @@ void optc3_init_odm(struct timing_generator *optc)
                        OPTC_MEM_SEL, 0);
        optc1->opp_count = 1;
 }
+void optc31_set_static_screen_control(
+       struct timing_generator *optc,
+       uint32_t event_triggers,
+       uint32_t num_frames)
+{
+       struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t framecount;
+       uint32_t events;
+
+       if (num_frames > 0xFF)
+               num_frames = 0xFF;
+       REG_GET_2(OTG_STATIC_SCREEN_CONTROL,
+                       OTG_STATIC_SCREEN_EVENT_MASK, &events,
+                       OTG_STATIC_SCREEN_FRAME_COUNT, &framecount);
+
+       if (events == event_triggers && num_frames == framecount)
+               return;
+       if ((event_triggers & STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN)
+                       != 0)
+               event_triggers = event_triggers &
+               ~STATIC_SCREEN_EVENT_MASK_DRR_DOUBLE_BUFFER_UPDATE_EN;
+
+       REG_UPDATE_2(OTG_STATIC_SCREEN_CONTROL,
+                       OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
+                       OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
+}
 
 static struct timing_generator_funcs dcn31_tg_funcs = {
                .validate_timing = optc1_validate_timing,
@@ -266,7 +293,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = {
                .set_drr = optc31_set_drr,
                .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
                .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
+               .set_static_screen_control = optc31_set_static_screen_control,
                .program_stereo = optc1_program_stereo,
                .is_stereo_left_eye = optc1_is_stereo_left_eye,
                .tg_init = optc3_tg_init,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
index 30b81a4..5fc6c63 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -263,5 +263,8 @@ bool optc31_immediate_disable_crtc(struct timing_generator *optc);
 void optc31_set_drr(struct timing_generator *optc, const struct drr_params *params);
 
 void optc3_init_odm(struct timing_generator *optc);
-
+void optc31_set_static_screen_control(
+       struct timing_generator *optc,
+       uint32_t event_triggers,
+       uint32_t num_frames);
 #endif /* __DC_OPTC_DCN31_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index 5b6c2d9..31feb4b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -66,9 +66,9 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
        .prepare_bandwidth = dcn20_prepare_bandwidth,
        .optimize_bandwidth = dcn20_optimize_bandwidth,
        .update_bandwidth = dcn20_update_bandwidth,
-       .set_drr = dcn10_set_drr,
+       .set_drr = dcn31_set_drr,
        .get_position = dcn10_get_position,
-       .set_static_screen_control = dcn10_set_static_screen_control,
+       .set_static_screen_control = dcn31_set_static_screen_control,
        .setup_stereo = dcn10_setup_stereo,
        .set_avmute = dcn30_set_avmute,
        .log_hw_state = dcn10_log_hw_state,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
index f246aab..41edbd6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c
@@ -228,7 +228,7 @@ static struct timing_generator_funcs dcn314_tg_funcs = {
                .set_drr = optc31_set_drr,
                .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
                .set_vtotal_min_max = optc1_set_vtotal_min_max,
-               .set_static_screen_control = optc1_set_static_screen_control,
+               .set_static_screen_control = optc31_set_static_screen_control,
                .program_stereo = optc1_program_stereo,
                .is_stereo_left_eye = optc1_is_stereo_left_eye,
                .tg_init = optc3_tg_init,