Update DNDI kernel and DNDI states on Sandybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index f8a52c3..fb8bba7 100644 (file)
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -2072,15 +2072,15 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
 
     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
-    sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
-    sampler_dndi[index].dw1.stmm_c2 = 0;
+    sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
+    sampler_dndi[index].dw1.stmm_c2 = 1;
     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
 
     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
-    sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
+    sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
 
     sampler_dndi[index].dw3.maximum_stmm = 128;
     sampler_dndi[index].dw3.multipler_for_vecm = 2;
@@ -2095,26 +2095,26 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
     sampler_dndi[index].dw4.stmm_shift_down = 0;
     sampler_dndi[index].dw4.minimum_stmm = 0;
 
-    sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
-    sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
-    sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
-    sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
+    sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
+    sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
+    sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
+    sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
 
     sampler_dndi[index].dw6.dn_enable = 1;
     sampler_dndi[index].dw6.di_enable = 1;
     sampler_dndi[index].dw6.di_partial = 0;
     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
-    sampler_dndi[index].dw6.dndi_stream_id = 1;
+    sampler_dndi[index].dw6.dndi_stream_id = 0;
     sampler_dndi[index].dw6.dndi_first_frame = 1;
     sampler_dndi[index].dw6.progressive_dn = 0;
-    sampler_dndi[index].dw6.fmd_tear_threshold = 32;
+    sampler_dndi[index].dw6.fmd_tear_threshold = 63;
     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
 
-    sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
-    sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
+    sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
+    sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
     sampler_dndi[index].dw7.vdi_walker_enable = 0;
-    sampler_dndi[index].dw7.column_width_minus1 = w / 16;
+    sampler_dndi[index].dw7.column_width_minus1 = 0;
 
     dri_bo_unmap(pp_context->sampler_state_table.bo);
 
@@ -2124,9 +2124,9 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
 
     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
-    pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
-    pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
-    pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
+    pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
+    pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
+    pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
 
     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
     pp_inline_parameter->grf5.number_blocks = w / 16;

diff --git a/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm b/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
index 69330ba..90089ac 100644 (file)
--- a/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
+++ b/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
@@ -80,6 +80,10 @@ TOP_FIELD_FIRST:
         mov (4)     mudMSGHDR_DN(1,%1*4+4)<1>   udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 1st field luma from current frame (line 1,3)
     }
 SAVE_DN_CURR:
+    $for (0; <nY_NUM_OF_ROWS/2; 1) {
+        mov (16) mubMSGHDR_DN(1, %1*16)<1>       ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16)
+    }
+        
     mov (2)     rMSGSRC.0<1>:ud        wORIX<2;2,1>:w               // X origin and Y origin
     mov (1)     rMSGSRC.2<1>:ud        nDPW_BLOCK_SIZE_DN:ud        // block width and height (16x4)
     mov (8)     mudMSGHDR_DN(0)<1>     rMSGSRC.0<8;8,1>:ud

diff --git a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
index 6c0474d..aee45d1 100644 (file)
--- a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
+++ b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
@@ -56,6 +56,10 @@
    { 0x00400001, 0x20500022, 0x00690580, 0x00000000 },
    { 0x00400001, 0x20600022, 0x006904e0, 0x00000000 },
    { 0x00400001, 0x20700022, 0x00690590, 0x00000000 },
+   { 0x00800001, 0x20400232, 0x00b104c0, 0x00000000 },
+   { 0x00800001, 0x20500232, 0x00b104d0, 0x00000000 },
+   { 0x00800001, 0x20600232, 0x00b104e0, 0x00000000 },
+   { 0x00800001, 0x20700232, 0x00b104f0, 0x00000000 },
    { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
    { 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
    { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
@@ -75,10 +79,10 @@
    { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 },
    { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 },
    { 0x00010220, 0x34001c00, 0x00001400, 0x00000008 },
-   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff70 },
+   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff68 },
    { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 },
    { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 },
-   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff6a },
+   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff62 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 },
    { 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 },

diff --git a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
index cb99eff..29003af 100644 (file)
--- a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
+++ b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
@@ -129,6 +129,10 @@
    { 0x00400001, 0x20500022, 0x00690580, 0x00000000 },
    { 0x00400001, 0x20600022, 0x006904e0, 0x00000000 },
    { 0x00400001, 0x20700022, 0x00690590, 0x00000000 },
+   { 0x00800001, 0x20400232, 0x00b104c0, 0x00000000 },
+   { 0x00800001, 0x20500232, 0x00b104d0, 0x00000000 },
+   { 0x00800001, 0x20600232, 0x00b104e0, 0x00000000 },
+   { 0x00800001, 0x20700232, 0x00b104f0, 0x00000000 },
    { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
    { 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
    { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
@@ -148,10 +152,10 @@
    { 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 },
    { 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 },
    { 0x00010220, 0x34001c00, 0x00001400, 0x00000008 },
-   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff70 },
+   { 0x00010220, 0x34001c00, 0x02001400, 0xffffff68 },
    { 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 },
    { 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 },
-   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff6a },
+   { 0x00000220, 0x34001c00, 0x00001400, 0xffffff62 },
    { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
    { 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 },
    { 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 },