>;
reg-names = "NN_REG","NN_SRAM","NN_MEM0",
"NN_MEM1","NN_RESET","NN_CLK";
+ nn_power_version = <2>;
nn_efuse = <0xff63003c 0x20>;
};
interrupts = <0 186 4>;
interrupt-names = "galcore";
reg = <0xff100000 0x800
- /*reg base value:0xff100000 */
0xff000000 0x400000
- /*Sram bse value:0xff000000*/
0xff63c118 0x0
0xff63c11c 0x0
- /*0xff63c118,0xff63c11c :nanoq mem regs*/
0xffd01088 0x0
- /*0xffd01088:reset reg*/
+ 0xff63c1c8 0x0
>;
+ reg-names = "NN_REG","NN_SRAM","NN_MEM0",
+ "NN_MEM1","NN_RESET","NN_CLK";
+ nn_power_version = <3>;
nn_efuse = <0xff63003c 0x20>;
};
aocec: aocec {
interrupts = <0 147 4>;
interrupt-names = "galcore";
reg = <0xff100000 0x800
- /*reg base value:0xff100000 */
0xff000000 0x400000
- /*Sram bse value:0xff000000*/
0xff63c118 0x0
0xff63c11c 0x0
- /*0xff63c118,0xff63c11c :nanoq mem regs*/
0xffd01088 0x0
- /*0xffd01088:reset reg*/
+ 0xff63c1c8 0x0
>;
+ reg-names = "NN_REG","NN_SRAM","NN_MEM0",
+ "NN_MEM1","NN_RESET","NN_CLK";
+ nn_power_version = <3>;
nn_efuse = <0xff63003c 0x20>;
};
sd_emmc_c: emmc@ffe07000 {
>;
reg-names = "NN_REG","NN_SRAM","NN_MEM0",
"NN_MEM1","NN_RESET","NN_CLK";
+ nn_power_version = <2>;
nn_efuse = <0xff63003c 0x20>;
};
interrupts = <0 186 4>;
interrupt-names = "galcore";
reg = <0x0 0xff100000 0x0 0x800
- /*reg base value:0xff100000 */
0x0 0xff000000 0x0 0x400000
- /*Sram bse value:0xff000000*/
0x0 0xff63c118 0x0 0x0
0x0 0xff63c11c 0x0 0x0
- /*0xff63c118,0xff63c11c :nanoq mem regs*/
0x0 0xffd01088 0x0 0x0
- /*0xffd01088:reset reg*/
+ 0x0 0xff63c1c8 0x0 0x0
>;
+ reg-names = "NN_REG","NN_SRAM","NN_MEM0",
+ "NN_MEM1","NN_RESET","NN_CLK";
+ nn_power_version = <3>;
nn_efuse = <0xff63003c 0x20>;
};
aocec: aocec {
interrupts = <0 147 4>;
interrupt-names = "galcore";
reg = <0x0 0xff100000 0x0 0x800
- /*reg base value:0xff100000 */
0x0 0xff000000 0x0 0x400000
- /*Sram bse value:0xff000000*/
0x0 0xff63c118 0x0 0x0
0x0 0xff63c11c 0x0 0x0
- /*0xff63c118,0xff63c11c :nanoq mem regs*/
0x0 0xffd01088 0x0 0x0
- /*0xffd01088:reset reg*/
+ 0x0 0xff63c1c8 0x0 0x0
>;
+ reg-names = "NN_REG","NN_SRAM","NN_MEM0",
+ "NN_MEM1","NN_RESET","NN_CLK";
+ nn_power_version = <3>;
nn_efuse = <0xff63003c 0x20>;
};
sd_emmc_c: emmc@ffe07000 {