+2010-12-14 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
+
+ * config/h8300/h8300.md (define_split) : Add condition for
+ "and with single_zero" splitter to handle 16-bit const operands.
+ * config/h8300/h8300.md (define_split) : Add condition for
+ "ior with single_one" splitter to handle 16-bit const operands.
+ * config/h8300/h8300.md (define_split) : Add condition for
+ "xor with single_one" splitter to handle 16-bit const operands.
+ * testsuite/gcc.dg/h8300-bit-insn-ice.c: New.
+
2010-12-13 Jan Hubicka <jh@suse.cz>
PR middle-end/45388
(and:QI (match_dup 1)
(match_dup 2)))]
{
- operands[0] = adjust_address (operands[0], QImode, 1);
- operands[1] = adjust_address (operands[1], QImode, 1);
+ if (abs (INTVAL (operands[2])) > 0xFF)
+ {
+ operands[0] = adjust_address (operands[0], QImode, 0);
+ operands[1] = adjust_address (operands[1], QImode, 0);
+ operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
+ }
+ else
+ {
+ operands[0] = adjust_address (operands[0], QImode, 1);
+ operands[1] = adjust_address (operands[1], QImode, 1);
+ }
})
(define_insn "bclrhi_msx"
(ior:QI (match_dup 1)
(match_dup 2)))]
{
- operands[0] = adjust_address (operands[0], QImode, 1);
- operands[1] = adjust_address (operands[1], QImode, 1);
+ if (abs (INTVAL (operands[2])) > 0xFF)
+ {
+ operands[0] = adjust_address (operands[0], QImode, 0);
+ operands[1] = adjust_address (operands[1], QImode, 0);
+ operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
+ }
+ else
+ {
+ operands[0] = adjust_address (operands[0], QImode, 1);
+ operands[1] = adjust_address (operands[1], QImode, 1);
+ }
})
(define_insn "bsethi_msx"
(xor:QI (match_dup 1)
(match_dup 2)))]
{
- operands[0] = adjust_address (operands[0], QImode, 1);
- operands[1] = adjust_address (operands[1], QImode, 1);
+ if (abs (INTVAL (operands[2])) > 0xFF)
+ {
+ operands[0] = adjust_address (operands[0], QImode, 0);
+ operands[1] = adjust_address (operands[1], QImode, 0);
+ operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
+ }
+ else
+ {
+ operands[0] = adjust_address (operands[0], QImode, 1);
+ operands[1] = adjust_address (operands[1], QImode, 1);
+ }
})
(define_insn "bnothi_msx"
--- /dev/null
+/* { dg-skip-if "" { "h8300*-*-*" } "*" "-msx*" } */
+/* ICE for bit instruction generation using 16-bit const */
+
+__extension__ struct st_mstp
+{
+ union
+ {
+ unsigned short WORD;
+ struct
+ {
+ unsigned char ACSE:1;
+ unsigned char _EXDMAC:1;
+ unsigned char _DMAC:1;
+ unsigned char _DTC:1;
+ unsigned char:2;
+ unsigned char _TMR23:1;
+ unsigned char _TMR01:1;
+ unsigned char:2;
+ unsigned char _DA:1;
+ unsigned char:1;
+ unsigned char _AD:1;
+ unsigned char:1;
+ unsigned char _TPUU:1;
+ unsigned char _TPUL:1;
+ } BIT;
+ } CRA;
+};
+#define MSTP (*(volatile struct st_mstp *)0xFFFDC8)
+#define MSTPA_EXDMA 0x4000
+#define MSTPA_AND 0xFEFF
+
+int
+main ()
+{
+ MSTP.CRA.WORD |= MSTPA_EXDMA;
+ MSTP.CRA.WORD ^= MSTPA_EXDMA;
+ MSTP.CRA.WORD &= MSTPA_AND;
+ return 0;
+}