[PowerPC] add testcase for vector add and shift

diff --git a/llvm/test/CodeGen/PowerPC/optimize-vector.ll b/llvm/test/CodeGen/PowerPC/optimize-vector.ll
new file mode 100644 (file)
index 0000000..6a2142d
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/optimize-vector.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+define dso_local <16 x i8> @x2(<16 x i8> noundef %x) {
+; CHECK-LABEL: x2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vspltisb v3, 1
+; CHECK-NEXT:    vslb v2, v2, v3
+; CHECK-NEXT:    blr
+entry:
+  %add = shl <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %add
+}
+
+define dso_local <8 x i16> @x2h(<8 x i16> noundef %x) {
+; CHECK-LABEL: x2h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vspltish v3, 1
+; CHECK-NEXT:    vslh v2, v2, v3
+; CHECK-NEXT:    blr
+entry:
+  %add = shl <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %add
+}
+
+define dso_local <4 x i32> @x2w(<4 x i32> noundef %x) {
+; CHECK-LABEL: x2w:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vspltisw v3, 1
+; CHECK-NEXT:    vslw v2, v2, v3
+; CHECK-NEXT:    blr
+entry:
+  %add = shl <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add
+}