net: phy: dp83867: Add device tree bindings and documentation

Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.

The original document was from:
    [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
new file mode 100644 (file)
index 0000000..cb77fdf
--- /dev/null
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -0,0 +1,25 @@
+* Texas Instruments - dp83867 Giga bit ethernet phy
+
+Required properties:
+       - reg - The ID number for the phy, usually a small integer
+       - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
+               for applicable values
+       - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
+               for applicable values
+       - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
+               for applicable values
+
+Default child nodes are standard Ethernet PHY device
+nodes as described in doc/devicetree/bindings/net/ethernet.txt
+
+Example:
+
+       ethernet-phy@0 {
+               reg = <0>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+               ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+       };
+
+Datasheet can be found:
+http://www.ti.com/product/DP83867IR/datasheet

diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
new file mode 100644 (file)
index 0000000..1843757
--- /dev/null
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -0,0 +1,35 @@
+/*
+ * TI DP83867 PHY drivers
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB       0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB       0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB       0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB       0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83867_RGMIIDCTL_250_PS       0x0
+#define DP83867_RGMIIDCTL_500_PS       0x1
+#define DP83867_RGMIIDCTL_750_PS       0x2
+#define DP83867_RGMIIDCTL_1_NS         0x3
+#define DP83867_RGMIIDCTL_1_25_NS      0x4
+#define DP83867_RGMIIDCTL_1_50_NS      0x5
+#define DP83867_RGMIIDCTL_1_75_NS      0x6
+#define DP83867_RGMIIDCTL_2_00_NS      0x7
+#define DP83867_RGMIIDCTL_2_25_NS      0x8
+#define DP83867_RGMIIDCTL_2_50_NS      0x9
+#define DP83867_RGMIIDCTL_2_75_NS      0xa
+#define DP83867_RGMIIDCTL_3_00_NS      0xb
+#define DP83867_RGMIIDCTL_3_25_NS      0xc
+#define DP83867_RGMIIDCTL_3_50_NS      0xd
+#define DP83867_RGMIIDCTL_3_75_NS      0xe
+#define DP83867_RGMIIDCTL_4_00_NS      0xf
+
+#endif