powerpc/40x: Add support for PPC40x boards with > 512MB SDRAM

This patch adds support for boards with more that 512MByte RAM. Currently
only 512MB of memory are enabled in the DCCR/ICCR real-mode cache
control registers. This patch now enables caching in real-mode for
2GByte.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c
index 08dfa8e6d86fa6a842474074f43d0b77e7d87fe6..65abfcfaaa9e72be187902357b3d29577fd06d28 100644 (file)
--- a/arch/powerpc/mm/40x_mmu.c
+++ b/arch/powerpc/mm/40x_mmu.c
@@ -84,8 +84,8 @@ void __init MMU_init_hw(void)
         * vectors and the kernel live in real-mode.
         */
 
-        mtspr(SPRN_DCCR, 0xF0000000);  /* 512 MB of data space at 0x0. */
-        mtspr(SPRN_ICCR, 0xF0000000);  /* 512 MB of instr. space at 0x0. */
+        mtspr(SPRN_DCCR, 0xFFFF0000);  /* 2GByte of data space at 0x0. */
+        mtspr(SPRN_ICCR, 0xFFFF0000);  /* 2GByte of instr. space at 0x0. */
 }
 
 #define LARGE_PAGE_SIZE_16M    (1<<24)