non-zero means yes, zero means no. Value type: ``uint32_t``
* ``PIPE_COMPUTE_CAP_SUBGROUP_SIZE``: The size of a basic execution unit in
threads. Also known as wavefront size, warp size or SIMD width.
+* ``PIPE_COMPUTE_CAP_ADDRESS_BITS``: The default compute device address space
+ size specified as an unsigned integer value in bits.
.. _pipe_bind:
uint32_t max_compute_units;
uint32_t images_supported;
uint32_t subgroup_size;
+ uint32_t address_bits;
} val;
const void *ptr;
int size;
ptr = &val.max_input_size;
size = sizeof(val.max_input_size);
break;
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+ val.address_bits = 32;
+ ptr = &val.address_bits;
+ size = sizeof(val.address_bits);
+ break;
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
val.max_mem_alloc_size = 1u << 31;
RET((uint32_t []) { screen->mp_count });
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+ RET((uint32_t []) { 32 });
default:
return 0;
}
RET((uint32_t []) { screen->mp_count_compute });
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+ RET((uint32_t []) { 64 });
default:
return 0;
}
*max_threads_per_block = 256;
}
return sizeof(uint64_t);
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+ if (ret) {
+ uint32_t *address_bits = ret;
+ address_bits[0] = 32;
+ if (rscreen->chip_class >= SI)
+ address_bits[0] = 64;
+ }
+ return 1 * sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
if (ret) {
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
break;
}
return 0;
*/
enum pipe_compute_cap
{
+ PIPE_COMPUTE_CAP_ADDRESS_BITS,
PIPE_COMPUTE_CAP_IR_TARGET,
PIPE_COMPUTE_CAP_GRID_DIMENSION,
PIPE_COMPUTE_CAP_MAX_GRID_SIZE,