I3510_EOR = 0x4a000000,
I3510_EON = 0x4a200000,
I3510_ANDS = 0x6a000000,
+
+ /* System instructions. */
+ DMB_ISH = 0xd50338bf,
+ DMB_LD = 0x00000100,
+ DMB_ST = 0x00000200,
} AArch64Insn;
static inline uint32_t tcg_in32(TCGContext *s)
tcg_out_mov(s, ext, orig_rl, rl);
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ static const uint32_t sync[] = {
+ [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST,
+ [TCG_MO_ST_ST] = DMB_ISH | DMB_ST,
+ [TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
+ [TCG_MO_LD_ST] = DMB_ISH | DMB_LD,
+ [TCG_MO_LD_ST | TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
+ };
+ tcg_out32(s, sync[a0 & TCG_MO_ALL]);
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
{ INDEX_op_muluh_i64, { "r", "r", "r" } },
{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};