ath10k: add bus type for each layout of coredump

For some hw version, it has more than one bus type, it need to add bus
type to distinguish different chip.

Tested-on: QCA6174 SDIO WLAN.RMH.4.4.1-00018-QCARMSWP-1

Signed-off-by: Wen Gong <wgong@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1569310030-834-2-git-send-email-wgong@codeaurora.org

diff --git a/drivers/net/wireless/ath/ath10k/coredump.c b/drivers/net/wireless/ath/ath10k/coredump.c
index 2a44980..fdc9739 100644 (file)
--- a/drivers/net/wireless/ath/ath10k/coredump.c
+++ b/drivers/net/wireless/ath/ath10k/coredump.c
@@ -968,6 +968,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA6174_HW_1_0_VERSION,
                .hw_rev = ATH10K_HW_QCA6174,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca6174_hw10_mem_regions,
                        .size = ARRAY_SIZE(qca6174_hw10_mem_regions),
@@ -976,6 +977,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA6174_HW_1_1_VERSION,
                .hw_rev = ATH10K_HW_QCA6174,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca6174_hw10_mem_regions,
                        .size = ARRAY_SIZE(qca6174_hw10_mem_regions),
@@ -984,6 +986,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA6174_HW_1_3_VERSION,
                .hw_rev = ATH10K_HW_QCA6174,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca6174_hw10_mem_regions,
                        .size = ARRAY_SIZE(qca6174_hw10_mem_regions),
@@ -992,6 +995,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA6174_HW_2_1_VERSION,
                .hw_rev = ATH10K_HW_QCA6174,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca6174_hw21_mem_regions,
                        .size = ARRAY_SIZE(qca6174_hw21_mem_regions),
@@ -1000,6 +1004,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA6174_HW_3_0_VERSION,
                .hw_rev = ATH10K_HW_QCA6174,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca6174_hw30_mem_regions,
                        .size = ARRAY_SIZE(qca6174_hw30_mem_regions),
@@ -1008,6 +1013,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA6174_HW_3_2_VERSION,
                .hw_rev = ATH10K_HW_QCA6174,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca6174_hw30_mem_regions,
                        .size = ARRAY_SIZE(qca6174_hw30_mem_regions),
@@ -1016,6 +1022,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA9377_HW_1_1_DEV_VERSION,
                .hw_rev = ATH10K_HW_QCA9377,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca6174_hw30_mem_regions,
                        .size = ARRAY_SIZE(qca6174_hw30_mem_regions),
@@ -1024,6 +1031,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA988X_HW_2_0_VERSION,
                .hw_rev = ATH10K_HW_QCA988X,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca988x_hw20_mem_regions,
                        .size = ARRAY_SIZE(qca988x_hw20_mem_regions),
@@ -1032,6 +1040,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA9984_HW_1_0_DEV_VERSION,
                .hw_rev = ATH10K_HW_QCA9984,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca9984_hw10_mem_regions,
                        .size = ARRAY_SIZE(qca9984_hw10_mem_regions),
@@ -1040,6 +1049,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA9888_HW_2_0_DEV_VERSION,
                .hw_rev = ATH10K_HW_QCA9888,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca9984_hw10_mem_regions,
                        .size = ARRAY_SIZE(qca9984_hw10_mem_regions),
@@ -1048,6 +1058,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA99X0_HW_2_0_DEV_VERSION,
                .hw_rev = ATH10K_HW_QCA99X0,
+               .bus = ATH10K_BUS_PCI,
                .region_table = {
                        .regions = qca99x0_hw20_mem_regions,
                        .size = ARRAY_SIZE(qca99x0_hw20_mem_regions),
@@ -1056,6 +1067,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = QCA4019_HW_1_0_DEV_VERSION,
                .hw_rev = ATH10K_HW_QCA4019,
+               .bus = ATH10K_BUS_AHB,
                .region_table = {
                        .regions = qca4019_hw10_mem_regions,
                        .size = ARRAY_SIZE(qca4019_hw10_mem_regions),
@@ -1064,6 +1076,7 @@ static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
        {
                .hw_id = WCN3990_HW_1_0_DEV_VERSION,
                .hw_rev = ATH10K_HW_WCN3990,
+               .bus = ATH10K_BUS_SNOC,
                .region_table = {
                        .regions = wcn399x_hw10_mem_regions,
                        .size = ARRAY_SIZE(wcn399x_hw10_mem_regions),
@@ -1111,7 +1124,8 @@ const struct ath10k_hw_mem_layout *ath10k_coredump_get_mem_layout(struct ath10k
 
        for (i = 0; i < ARRAY_SIZE(hw_mem_layouts); i++) {
                if (ar->target_version == hw_mem_layouts[i].hw_id &&
-                   ar->hw_rev == hw_mem_layouts[i].hw_rev)
+                   ar->hw_rev == hw_mem_layouts[i].hw_rev &&
+                   hw_mem_layouts[i].bus == ar->hif.bus)
                        return &hw_mem_layouts[i];
        }
 

diff --git a/drivers/net/wireless/ath/ath10k/coredump.h b/drivers/net/wireless/ath/ath10k/coredump.h
index e760ce1..42404e2 100644 (file)
--- a/drivers/net/wireless/ath/ath10k/coredump.h
+++ b/drivers/net/wireless/ath/ath10k/coredump.h
@@ -156,6 +156,7 @@ struct ath10k_mem_region {
 struct ath10k_hw_mem_layout {
        u32 hw_id;
        u32 hw_rev;
+       enum ath10k_bus bus;
 
        struct {
                const struct ath10k_mem_region *regions;