radeonsi: move VGT_VERTEX_REUSE_BLOCK_CNTL into shader states for Polaris

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index d862e26..e5da730 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -251,7 +251,6 @@ void si_begin_new_cs(struct si_context *ctx)
        ctx->last_multi_vgt_param = -1;
        ctx->last_rast_prim = -1;
        ctx->last_sc_line_stipple = ~0;
-       ctx->last_vtx_reuse_depth = -1;
        ctx->emit_scratch_reloc = true;
        ctx->last_ls = NULL;
        ctx->last_tcs = NULL;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 13b1e34..18cd25c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -326,7 +326,6 @@ struct si_context {
        int                     last_multi_vgt_param;
        int                     last_rast_prim;
        unsigned                last_sc_line_stipple;
-       int                     last_vtx_reuse_depth;
        int                     current_rast_prim; /* primitive type after TES, GS */
        bool                    gs_tri_strip_adj_fix;
 

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index f0bd930..5313a4d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -468,25 +468,6 @@ static void si_emit_draw_registers(struct si_context *sctx,
        unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
        unsigned ia_multi_vgt_param, num_patches = 0;
 
-       /* Polaris needs different VTX_REUSE_DEPTH settings depending on
-        * whether the "fractional odd" tessellation spacing is used.
-        */
-       if (sctx->b.family >= CHIP_POLARIS10) {
-               struct si_shader_selector *tes = sctx->tes_shader.cso;
-               unsigned vtx_reuse_depth = 30;
-
-               if (tes &&
-                   tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
-                   PIPE_TESS_SPACING_FRACTIONAL_ODD)
-                       vtx_reuse_depth = 14;
-
-               if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
-                       radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
-                                              vtx_reuse_depth);
-                       sctx->last_vtx_reuse_depth = vtx_reuse_depth;
-               }
-       }
-
        if (sctx->tes_shader.cso)
                si_emit_derived_tess_state(sctx, info, &num_patches);
 

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 02f8d6c..94fffdb 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -331,6 +331,45 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
                       S_028B6C_DISTRIBUTION_MODE(distribution_mode));
 }
 
+/* Polaris needs different VTX_REUSE_DEPTH settings depending on
+ * whether the "fractional odd" tessellation spacing is used.
+ *
+ * Possible VGT configurations and which state should set the register:
+ *
+ *   Reg set in | VGT shader configuration   | Value
+ * ------------------------------------------------------
+ *     VS as VS | VS                         | 30
+ *     VS as ES | ES -> GS -> VS             | 30
+ *    TES as VS | LS -> HS -> VS             | 14 or 30
+ *    TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
+ */
+static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
+                                        struct si_shader *shader,
+                                        struct si_pm4_state *pm4)
+{
+       unsigned type = shader->selector->type;
+
+       if (sscreen->b.family < CHIP_POLARIS10)
+               return;
+
+       /* VS as VS, or VS as ES: */
+       if ((type == PIPE_SHADER_VERTEX &&
+            !shader->key.as_ls &&
+            !shader->is_gs_copy_shader) ||
+           /* TES as VS, or TES as ES: */
+           type == PIPE_SHADER_TESS_EVAL) {
+               unsigned vtx_reuse_depth = 30;
+
+               if (type == PIPE_SHADER_TESS_EVAL &&
+                   shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
+                   PIPE_TESS_SPACING_FRACTIONAL_ODD)
+                       vtx_reuse_depth = 14;
+
+               si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
+                              vtx_reuse_depth);
+       }
+}
+
 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
 {
        if (shader->pm4)
@@ -438,6 +477,8 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
 
        if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
                si_set_tesseval_regs(sscreen, shader, pm4);
+
+       polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
 }
 
 /**
@@ -625,6 +666,8 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
 
        if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
                si_set_tesseval_regs(sscreen, shader, pm4);
+
+       polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
 }
 
 static unsigned si_get_ps_num_interp(struct si_shader *ps)