drm/amd/display: Reverted DSC programming sequence change

[HOW&WHY]
Revert a previous commit by moving DSC programming back to before link
enablement.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jayendran Ramani <Jayendran.Ramani@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Nagulendran, Iswara <Iswara.Nagulendran@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 4ab27e2..7f8da6a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4299,6 +4299,19 @@ void core_link_enable_stream(
                if (pipe_ctx->stream->dpms_off)
                        return;
 
+               /* Have to setup DSC before DIG FE and BE are connected (which happens before the
+                * link training). This is to make sure the bandwidth sent to DIG BE won't be
+                * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
+                * will be automatically set at a later time when the video is enabled
+                * (DP_VID_STREAM_EN = 1).
+                */
+               if (pipe_ctx->stream->timing.flags.DSC) {
+                       if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
+                               dc_is_virtual_signal(pipe_ctx->stream->signal))
+                       dp_set_dsc_enable(pipe_ctx, true);
+
+               }
+
                status = enable_link(state, pipe_ctx);
 
                if (status != DC_OK) {

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index fe346e9..801206a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1577,19 +1577,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
        if (dc_is_dp_signal(pipe_ctx->stream->signal))
                dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
 
-       /* Have to setup DSC before DIG FE and BE are connected (which happens before the
-        * link training). This is to make sure the bandwidth sent to DIG BE won't be
-        * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
-        * will be automatically set at a later time when the video is enabled
-        * (DP_VID_STREAM_EN = 1).
-        */
-       if (pipe_ctx->stream->timing.flags.DSC) {
-               if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
-                       dc_is_virtual_signal(pipe_ctx->stream->signal))
-                       dp_set_dsc_enable(pipe_ctx, true);
-
-       }
-
        if (!stream->dpms_off) {
                if (dc->hwss.update_phy_state)
                        dc->hwss.update_phy_state(context, pipe_ctx, TX_ON_SYMCLK_ON);