cxgb3: Use PCI Express Capability accessors

Use PCI Express Capability access functions to simplify cxgb3 driver.

[bhelgaas: split cxgb3 and cxgb4 into separate patches]
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
index bff8a3cdd3dfb612965fc737f122150cb9e0e6dd..aef45d3113bac5e9200d4dae8efc9a754a38d18e 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
@@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap)
        unsigned int log2_width, pldsize;
        unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
 
-       pci_read_config_word(adap->pdev,
-                            adap->pdev->pcie_cap + PCI_EXP_DEVCTL,
-                            &val);
+       pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val);
        pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
 
        pci_read_config_word(adap->pdev, 0x2, &devid);
        if (devid == 0x37) {
-               pci_write_config_word(adap->pdev,
-                                     adap->pdev->pcie_cap + PCI_EXP_DEVCTL,
-                                     val & ~PCI_EXP_DEVCTL_READRQ &
-                                     ~PCI_EXP_DEVCTL_PAYLOAD);
+               pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL,
+                                          val & ~PCI_EXP_DEVCTL_READRQ &
+                                          ~PCI_EXP_DEVCTL_PAYLOAD);
                pldsize = 0;
        }
 
-       pci_read_config_word(adap->pdev, adap->pdev->pcie_cap + PCI_EXP_LNKCTL,
-                            &val);
+       pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val);
 
        fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
        fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
@@ -3425,15 +3421,13 @@ out_err:
 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
 {
        static unsigned short speed_map[] = { 33, 66, 100, 133 };
-       u32 pci_mode, pcie_cap;
+       u32 pci_mode;
 
-       pcie_cap = pci_pcie_cap(adapter->pdev);
-       if (pcie_cap) {
+       if (pci_is_pcie(adapter->pdev)) {
                u16 val;
 
                p->variant = PCI_VARIANT_PCIE;
-               pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
-                                       &val);
+               pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
                p->width = (val >> 4) & 0x3f;
                return;
        }