intel/rt: Add a pass to lower the new ray-tracing intrinsics

The new intrinsics we added for doing address calculations are all
things we fetch from the RT_DISPATCH_GLOBALS struct.  We could emit an
RT_DISPATCH_GLOBALS load at every point we want it and trust NIR to CSE
it for us but it's easier to use intermediate intrinsics.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 6b9300d..7baced4 100644 (file)
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -94,8 +94,10 @@ COMPILER_FILES = \
        compiler/brw_nir_lower_cs_intrinsics.c \
        compiler/brw_nir_lower_image_load_store.c \
        compiler/brw_nir_lower_mem_access_bit_sizes.c \
+       compiler/brw_nir_lower_rt_intrinsics.c \
        compiler/brw_nir_lower_scoped_barriers.c \
        compiler/brw_nir_opt_peephole_ffma.c \
+       compiler/brw_nir_rt.h \
        compiler/brw_nir_rt_builder.h \
        compiler/brw_nir_tcs_workarounds.c \
        compiler/brw_packed_float.c \

diff --git a/src/intel/compiler/brw_nir_lower_rt_intrinsics.c b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c
new file mode 100644 (file)
index 0000000..0b06f9e
--- /dev/null
+++ b/src/intel/compiler/brw_nir_lower_rt_intrinsics.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "brw_nir_rt.h"
+#include "brw_nir_rt_builder.h"
+
+static void
+lower_rt_intrinsics_impl(nir_function_impl *impl,
+                         const struct gen_device_info *devinfo)
+{
+   nir_builder build;
+   nir_builder_init(&build, impl);
+   nir_builder *b = &build;
+
+   b->cursor = nir_before_block(nir_start_block(b->impl));
+
+   struct brw_nir_rt_globals_defs globals;
+   brw_nir_rt_load_globals(b, &globals);
+
+   nir_foreach_block(block, impl) {
+      nir_foreach_instr_safe(instr, block) {
+         if (instr->type != nir_instr_type_intrinsic)
+            continue;
+
+         nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+
+         b->cursor = nir_after_instr(&intrin->instr);
+
+         nir_ssa_def *sysval = NULL;
+         switch (intrin->intrinsic) {
+         case nir_intrinsic_load_ray_base_mem_addr_intel:
+            sysval = globals.base_mem_addr;
+            break;
+
+         case nir_intrinsic_load_ray_hw_stack_size_intel:
+            sysval = nir_imul_imm(b, globals.hw_stack_size, 64);
+            break;
+
+         case nir_intrinsic_load_ray_sw_stack_size_intel:
+            sysval = nir_imul_imm(b, globals.sw_stack_size, 64);
+            break;
+
+         case nir_intrinsic_load_ray_num_dss_rt_stacks_intel:
+            sysval = globals.num_dss_rt_stacks;
+            break;
+
+         default:
+            continue;
+         }
+
+         if (sysval) {
+            nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
+                                     nir_src_for_ssa(sysval));
+            nir_instr_remove(&intrin->instr);
+         }
+      }
+   }
+
+   nir_metadata_preserve(impl, nir_metadata_block_index |
+                               nir_metadata_dominance);
+}
+
+void
+brw_nir_lower_rt_intrinsics(nir_shader *nir,
+                            const struct gen_device_info *devinfo)
+{
+   nir_foreach_function(function, nir) {
+      if (function->impl)
+         lower_rt_intrinsics_impl(function->impl, devinfo);
+   }
+}

diff --git a/src/intel/compiler/brw_nir_rt.h b/src/intel/compiler/brw_nir_rt.h
new file mode 100644 (file)
index 0000000..da08151
--- /dev/null
+++ b/src/intel/compiler/brw_nir_rt.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_NIR_RT_H
+#define BRW_NIR_RT_H
+
+#include "brw_nir.h"
+#include "brw_rt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void brw_nir_lower_rt_intrinsics(nir_shader *shader,
+                                 const struct gen_device_info *devinfo);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BRW_NIR_RT_H */

diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index 8f00106..c7325fa 100644 (file)
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -85,8 +85,10 @@ libintel_compiler_files = files(
   'brw_nir_lower_alpha_to_coverage.c',
   'brw_nir_lower_image_load_store.c',
   'brw_nir_lower_mem_access_bit_sizes.c',
+  'brw_nir_lower_rt_intrinsics.c',
   'brw_nir_lower_scoped_barriers.c',
   'brw_nir_opt_peephole_ffma.c',
+  'brw_nir_rt.h',
   'brw_nir_rt_builder.h',
   'brw_nir_tcs_workarounds.c',
   'brw_nir_clamp_image_1d_2d_array_sizes.c',