net: lx2160a.c: Update to set ECx_PMUX precedence

As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.

Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index e610528..596b88d 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1147,15 +1147,15 @@ int arch_early_init_r(void)
         * EC*_PMUX(rgmii) bits in RCW.
         * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
         * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
-        * Now if a dpmac is enabled by serdes bits then it takes precedence
-        * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
-        * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
-        * then the dpmac is SGMII and not RGMII.
+        * Now if a dpmac is enabled as RGMII through ECx_PMUX then it takes
+        * precedence over SerDes protocol. i.e. in LX2160A if we select serdes
+        * protocol that configures dpmac17 as SGMII and set the EC1_PMUX as
+        * RGMII, then the dpmac is RGMII and not SGMII.
         *
-        * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
-        * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
-        * or not? if it is (fsl_serdes_init has already enabled the dpmac),
-        * then don't enable it.
+        * Therefore, even thought fsl_rgmii_init is after fsl_serdes_init
+        * function of SOC, the dpmac will be enabled as RGMII even if it was
+        * also enabled before as SGMII. If ECx_PMUX is not configured for
+        * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init().
         */
        fsl_rgmii_init();
 #endif

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index baa9fa8..24a64b7 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -396,7 +396,7 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_EC2_REGSR  27
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK      0x00000003
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT     0
-#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK      0x00000007
+#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK      0x0000000C
 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT     2
 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x001F0000
 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16

diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c
index 1e62c64..e57f1a1 100644 (file)
--- a/drivers/net/ldpaa_eth/lx2160a.c
+++ b/drivers/net/ldpaa_eth/lx2160a.c
@@ -92,7 +92,7 @@ void fsl_rgmii_init(void)
                & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
        ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
 
-       if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV))
+       if (!ec)
                wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
 #endif
 
@@ -101,7 +101,7 @@ void fsl_rgmii_init(void)
                & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
        ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
 
-       if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV))
+       if (!ec)
                wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
 #endif
 }