/* r0-r127 inclusive, as pairs of 16-bits, gives 256 registers */
#define AGX_NUM_REGS (256)
+/* u0-u255 inclusive, as pairs of 16-bits */
+#define AGX_NUM_UNIFORMS (512)
+
enum agx_index_type {
AGX_INDEX_NULL = 0,
AGX_INDEX_NORMAL = 1,
}
static inline agx_index
-agx_immediate(uint16_t imm)
+agx_immediate(uint32_t imm)
{
+ assert(imm < (1 << 16) && "overflowed immediate");
+
return (agx_index) {
.value = imm,
.size = AGX_SIZE_16,
/* in half-words, specify r0h as 1, r1 as 2... */
static inline agx_index
-agx_register(uint8_t imm, enum agx_size size)
+agx_register(uint32_t imm, enum agx_size size)
{
+ assert(imm < AGX_NUM_REGS);
+
return (agx_index) {
.value = imm,
.size = size,
/* Also in half-words */
static inline agx_index
-agx_uniform(uint8_t imm, enum agx_size size)
+agx_uniform(uint32_t imm, enum agx_size size)
{
+ assert(imm < AGX_NUM_UNIFORMS);
+
return (agx_index) {
.value = imm,
.size = size,
((value >> 6) << 10);
} else if (src.type == AGX_INDEX_UNIFORM) {
assert(size == AGX_SIZE_16 || size == AGX_SIZE_32);
- assert(value < 0x200);
+ assert(value < AGX_NUM_UNIFORMS);
return
(value & BITFIELD_MASK(6)) |
- ((value >> 8) << 6) |
+ ((value & BITFIELD_BIT(8)) ? (1 << 6) : 0) |
((size == AGX_SIZE_32) ? (1 << 7) : 0) |
(0x1 << 8) |
(((value >> 6) & BITFIELD_MASK(2)) << 10);