--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=LE
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=BE
+
+define <4 x i32> @fsext_v4i32(<4 x i8>* %a) {
+; LE-LABEL: fsext_v4i32:
+; LE: // %bb.0:
+; LE-NEXT: ldrsb w8, [x0]
+; LE-NEXT: ldrsb w9, [x0, #1]
+; LE-NEXT: ldrsb w10, [x0, #2]
+; LE-NEXT: ldrsb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.s[1], w9
+; LE-NEXT: mov v0.s[2], w10
+; LE-NEXT: mov v0.s[3], w11
+; LE-NEXT: ret
+;
+; BE-LABEL: fsext_v4i32:
+; BE: // %bb.0:
+; BE-NEXT: ldrsb w8, [x0]
+; BE-NEXT: ldrsb w9, [x0, #1]
+; BE-NEXT: ldrsb w10, [x0, #2]
+; BE-NEXT: ldrsb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.s[1], w9
+; BE-NEXT: mov v0.s[2], w10
+; BE-NEXT: mov v0.s[3], w11
+; BE-NEXT: rev64 v0.4s, v0.4s
+; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = sext <4 x i8> %x to <4 x i32>
+ ret <4 x i32> %y
+}
+
+define <4 x i32> @fzext_v4i32(<4 x i8>* %a) {
+; LE-LABEL: fzext_v4i32:
+; LE: // %bb.0:
+; LE-NEXT: ldrb w8, [x0]
+; LE-NEXT: ldrb w9, [x0, #1]
+; LE-NEXT: ldrb w10, [x0, #2]
+; LE-NEXT: ldrb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.s[1], w9
+; LE-NEXT: mov v0.s[2], w10
+; LE-NEXT: mov v0.s[3], w11
+; LE-NEXT: ret
+;
+; BE-LABEL: fzext_v4i32:
+; BE: // %bb.0:
+; BE-NEXT: ldrb w8, [x0]
+; BE-NEXT: ldrb w9, [x0, #1]
+; BE-NEXT: ldrb w10, [x0, #2]
+; BE-NEXT: ldrb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.s[1], w9
+; BE-NEXT: mov v0.s[2], w10
+; BE-NEXT: mov v0.s[3], w11
+; BE-NEXT: rev64 v0.4s, v0.4s
+; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = zext <4 x i8> %x to <4 x i32>
+ ret <4 x i32> %y
+}
+
+define i32 @loadExt.i32(<4 x i8>* %ref) {
+; CHECK-LABEL: loadExt.i32:
+; CHECK: ldrb
+; LE-LABEL: loadExt.i32:
+; LE: // %bb.0:
+; LE-NEXT: ldrb w0, [x0]
+; LE-NEXT: ret
+;
+; BE-LABEL: loadExt.i32:
+; BE: // %bb.0:
+; BE-NEXT: ldrb w0, [x0]
+; BE-NEXT: ret
+ %a = load <4 x i8>, <4 x i8>* %ref
+ %vecext = extractelement <4 x i8> %a, i32 0
+ %conv = zext i8 %vecext to i32
+ ret i32 %conv
+}
+
+define <4 x i16> @fsext_v4i16(<4 x i8>* %a) {
+; LE-LABEL: fsext_v4i16:
+; LE: // %bb.0:
+; LE-NEXT: ldrsb w8, [x0]
+; LE-NEXT: ldrsb w9, [x0, #1]
+; LE-NEXT: ldrsb w10, [x0, #2]
+; LE-NEXT: ldrsb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.h[1], w9
+; LE-NEXT: mov v0.h[2], w10
+; LE-NEXT: mov v0.h[3], w11
+; LE-NEXT: // kill: def $d0 killed $d0 killed $q0
+; LE-NEXT: ret
+;
+; BE-LABEL: fsext_v4i16:
+; BE: // %bb.0:
+; BE-NEXT: ldrsb w8, [x0]
+; BE-NEXT: ldrsb w9, [x0, #1]
+; BE-NEXT: ldrsb w10, [x0, #2]
+; BE-NEXT: ldrsb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.h[1], w9
+; BE-NEXT: mov v0.h[2], w10
+; BE-NEXT: mov v0.h[3], w11
+; BE-NEXT: rev64 v0.4h, v0.4h
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = sext <4 x i8> %x to <4 x i16>
+ ret <4 x i16> %y
+}
+
+define <4 x i16> @fzext_v4i16(<4 x i8>* %a) {
+; LE-LABEL: fzext_v4i16:
+; LE: // %bb.0:
+; LE-NEXT: ldrb w8, [x0]
+; LE-NEXT: ldrb w9, [x0, #1]
+; LE-NEXT: ldrb w10, [x0, #2]
+; LE-NEXT: ldrb w11, [x0, #3]
+; LE-NEXT: fmov s0, w8
+; LE-NEXT: mov v0.h[1], w9
+; LE-NEXT: mov v0.h[2], w10
+; LE-NEXT: mov v0.h[3], w11
+; LE-NEXT: // kill: def $d0 killed $d0 killed $q0
+; LE-NEXT: ret
+;
+; BE-LABEL: fzext_v4i16:
+; BE: // %bb.0:
+; BE-NEXT: ldrb w8, [x0]
+; BE-NEXT: ldrb w9, [x0, #1]
+; BE-NEXT: ldrb w10, [x0, #2]
+; BE-NEXT: ldrb w11, [x0, #3]
+; BE-NEXT: fmov s0, w8
+; BE-NEXT: mov v0.h[1], w9
+; BE-NEXT: mov v0.h[2], w10
+; BE-NEXT: mov v0.h[3], w11
+; BE-NEXT: rev64 v0.4h, v0.4h
+; BE-NEXT: ret
+ %x = load <4 x i8>, <4 x i8>* %a
+ %y = zext <4 x i8> %x to <4 x i16>
+ ret <4 x i16> %y
+}