drm/i915: Implement WA 14011294188

Although the WA description targets the platforms it is a workaround
for the affected PCHs, that is why it is being checked.

v2: excluding DG1 fake PCH from WA

BSpec: 52890
BSpec: 53273
BSpec: 52888
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200727164729.28836-1-jose.souza@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0c713e83274dd061147d20c2e83e25adca10aa79..788bd4516365a8c53d3a096b6a4bb9417a387dda 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5302,6 +5302,12 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+       /* Wa_14011294188:ehl,jsl,tgl,rkl */
+       if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
+           INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
+               intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
+                            PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
+
        /* 1. Enable PCH reset handshake. */
        intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d31f3bf63457227cb506120764892685981e08..5eae593ee784fe03dd0f620c59002e2b08a48bd4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8730,6 +8730,7 @@ enum {
 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
+#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
 #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
 #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)