clk: samsung: clk-pll: Add support for pll1417x

pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
It is similar enough to pll0822x that practically the same code can
handle both. The difference that's to be noted is that when defining a
pl1417x PLL, the "con" parameter of the PLL macro should be set to the
CON1 register instead of CON3, like this:

    PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
        PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
        NULL),

Signed-off-by: David Virag <virag.david003@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211206153124.427102-6-virag.david003@gmail.com

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 83d1b03647db8432a9a584e8a4391023d6b2309a..70cdc87f714ee5a84da76c76e8440e4df5a53620 100644 (file)
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
                else
                        init.ops = &samsung_pll35xx_clk_ops;
                break;
+       case pll_1417x:
        case pll_0822x:
                pll->enable_offs = PLL0822X_ENABLE_SHIFT;
                pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;

diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a739f2b7ae80939f41d034ebbae94654ff05d0e1..c83a20195f6da61964897ef20b78d6759d46df84 100644 (file)
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -32,6 +32,7 @@ enum samsung_pll_type {
        pll_2550xx,
        pll_2650x,
        pll_2650xx,
+       pll_1417x,
        pll_1450x,
        pll_1451x,
        pll_1452x,