pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info,
struct MALI_RENDERER_STATE *rsd)
{
+ assert((info->push.count & 3) == 0);
+
rsd->properties.uniform_buffer_count = info->ubo_count;
- rsd->properties.midgard.uniform_count = info->midgard.uniform_cutoff;
+ rsd->properties.midgard.uniform_count = info->push.count / 4;
rsd->properties.midgard.shader_has_side_effects = info->writes_global;
rsd->properties.midgard.fp_mode = MALI_FP_MODE_GL_INF_NAN_ALLOWED;
static struct lcra_state *
allocate_registers(compiler_context *ctx, bool *spilled)
{
- /* The number of vec4 work registers available depends on when the
- * uniforms start and the shader stage. By ABI we limit blend shaders
- * to 8 registers, should be lower XXX */
- int work_count = ctx->inputs->is_blend ? 8 :
- 16 - MAX2((ctx->info->midgard.uniform_cutoff - 8), 0);
+ /* The number of vec4 work registers available depends on the number of
+ * register-mapped uniforms and the shader stage. By ABI we limit blend
+ * shaders to 8 registers, should be lower XXX */
+ unsigned rmu = ctx->info->push.count / 4;
+ int work_count = ctx->inputs->is_blend ? 8 : 16 - MAX2(rmu - 8, 0);
/* No register allocation to do with no SSA */
static void
mir_demote_uniforms(compiler_context *ctx, unsigned new_cutoff)
{
- unsigned old_work_count =
- 16 - MAX2((ctx->info->midgard.uniform_cutoff - 8), 0);
+ unsigned uniforms = ctx->info->push.count / 4;
+ unsigned old_work_count = 16 - MAX2(uniforms - 8, 0);
unsigned work_count = 16 - MAX2((new_cutoff - 8), 0);
unsigned min_demote = SSA_FIXED_REGISTER(old_work_count);
unsigned max_demote = SSA_FIXED_REGISTER(work_count);
- ctx->info->midgard.uniform_cutoff = new_cutoff;
-
mir_foreach_block(ctx, _block) {
midgard_block *block = (midgard_block *) _block;
mir_foreach_instr_in_block(block, ins) {
}
}
}
+
+ ctx->info->push.count = MIN2(ctx->info->push.count, new_cutoff * 4);
}
/* Run register allocation in a loop, spilling until we succeed */
do {
if (spilled) {
signed spill_node = mir_choose_spill_node(ctx, l);
+ unsigned uniforms = ctx->info->push.count / 4;
/* It's a lot cheaper to demote uniforms to get more
* work registers than to spill to TLS. */
- if (l->spill_class == REG_CLASS_WORK &&
- ctx->info->midgard.uniform_cutoff > 8) {
-
- mir_demote_uniforms(ctx, MAX2(ctx->info->midgard.uniform_cutoff - 4, 8));
+ if (l->spill_class == REG_CLASS_WORK && uniforms > 8) {
+ mir_demote_uniforms(ctx, MAX2(uniforms - 4, 8));
} else if (spill_node == -1) {
fprintf(stderr, "ERROR: Failed to choose spill node\n");
lcra_free(l);
unsigned work_count = mir_work_heuristic(ctx, &analysis);
unsigned promoted_count = 24 - work_count;
+ /* Ensure we are 16 byte aligned to avoid underallocations */
mir_pick_ubo(&ctx->info->push, &analysis, promoted_count);
+ ctx->info->push.count = ALIGN_POT(ctx->info->push.count, 4);
/* First, figure out special indices a priori so we don't recompute a lot */
BITSET_WORD *special = mir_special_indices(ctx);
/* Should've taken into account when pushing */
assert(address < promoted_count);
-
- ctx->info->midgard.uniform_cutoff =
- MAX2(ctx->info->midgard.uniform_cutoff, address + 1);
unsigned promoted = SSA_FIXED_REGISTER(uniform_reg);
/* We do need the move for safety for a non-SSA dest, or if